sfc: Expand/correct comments on collector behaviour and function usage
Document exactly which registers and functions have special behaviour, and why races on writes to descriptor pointers are safe. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
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Ben Hutchings
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@ -22,28 +22,39 @@
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*
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* Notes on locking strategy:
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*
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* Most NIC registers require 16-byte (or 8-byte, for SRAM) atomic writes
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* which necessitates locking.
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* Under normal operation few writes to NIC registers are made and these
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* registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
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* cased to allow 4-byte (hence lockless) accesses.
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* Most CSRs are 128-bit (oword) and therefore cannot be read or
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* written atomically. Access from the host is buffered by the Bus
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* Interface Unit (BIU). Whenever the host reads from the lowest
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* address of such a register, or from the address of a different such
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* register, the BIU latches the register's value. Subsequent reads
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* from higher addresses of the same register will read the latched
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* value. Whenever the host writes part of such a register, the BIU
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* collects the written value and does not write to the underlying
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* register until all 4 dwords have been written. A similar buffering
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* scheme applies to host access to the NIC's 64-bit SRAM.
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*
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* It *is* safe to write to these 4-byte registers in the middle of an
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* access to an 8-byte or 16-byte register. We therefore use a
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* spinlock to protect accesses to the larger registers, but no locks
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* for the 4-byte registers.
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* Access to different CSRs and 64-bit SRAM words must be serialised,
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* since interleaved access can result in lost writes or lost
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* information from read-to-clear fields. We use efx_nic::biu_lock
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* for this. (We could use separate locks for read and write, but
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* this is not normally a performance bottleneck.)
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*
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* A write barrier is needed to ensure that DW3 is written after DW0/1/2
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* due to the way the 16byte registers are "collected" in the BIU.
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* The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
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* 128-bit but are special-cased in the BIU to avoid the need for
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* locking in the host:
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*
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* We also lock when carrying out reads, to ensure consistency of the
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* data (made possible since the BIU reads all 128 bits into a cache).
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* Reads are very rare, so this isn't a significant performance
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* impact. (Most data transferred from NIC to host is DMAed directly
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* into host memory).
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*
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* I/O BAR access uses locks for both reads and writes (but is only provided
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* for testing purposes).
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* - They are write-only.
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* - The semantics of writing to these registers are such that
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* replacing the low 96 bits with zero does not affect functionality.
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* - If the host writes to the last dword address of such a register
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* (i.e. the high 32 bits) the underlying register will always be
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* written. If the collector does not hold values for the low 96
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* bits of the register, they will be written as zero. Writing to
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* the last qword does not have this effect and must not be done.
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* - If the host writes to the address of any other part of such a
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* register while the collector already holds values for some other
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* register, the write is discarded and the collector maintains its
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* current state.
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*/
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#if BITS_PER_LONG == 64
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@ -72,7 +83,7 @@ static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
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return (__force __le32)__raw_readl(efx->membase + reg);
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}
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/* Writes to a normal 16-byte Efx register, locking as appropriate. */
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/* Write a normal 128-bit CSR, locking as appropriate. */
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static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg)
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{
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@ -98,8 +109,7 @@ static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Write an 8-byte NIC SRAM entry through the supplied mapping,
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* locking as appropriate. */
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/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
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static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
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efx_qword_t *value, unsigned int index)
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{
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@ -122,29 +132,19 @@ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Write dword to NIC register that allows partial writes
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*
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* Some registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
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* TX_DESC_UPD_REG) can be written to as a single dword. This allows
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* for lockless writes.
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*/
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/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
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static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg)
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{
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netif_vdbg(efx, hw, efx->net_dev,
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"writing partial register %x with "EFX_DWORD_FMT"\n",
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"writing register %x with "EFX_DWORD_FMT"\n",
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reg, EFX_DWORD_VAL(*value));
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/* No lock required */
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_efx_writed(efx, value->u32[0], reg);
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}
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/* Read from a NIC register
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*
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* This reads an entire 16-byte register in one go, locking as
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* appropriate. It is essential to read the first dword first, as this
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* prompts the NIC to load the current value into the shadow register.
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*/
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/* Read a 128-bit CSR, locking as appropriate. */
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static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg)
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{
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@ -163,8 +163,7 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
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EFX_OWORD_VAL(*value));
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}
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/* Read an 8-byte SRAM entry through supplied mapping,
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* locking as appropriate. */
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/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
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static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
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efx_qword_t *value, unsigned int index)
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{
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@ -186,7 +185,7 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
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addr, EFX_QWORD_VAL(*value));
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}
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/* Read dword from register that allows partial writes (sic) */
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/* Read a 32-bit CSR or SRAM */
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static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg)
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{
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@ -196,28 +195,28 @@ static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
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reg, EFX_DWORD_VAL(*value));
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}
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/* Write to a register forming part of a table */
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/* Write a 128-bit CSR forming part of a table */
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static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Read to a register forming part of a table */
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/* Read a 128-bit CSR forming part of a table */
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static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Write to a dword register forming part of a table */
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/* Write a 32-bit CSR forming part of a table, or 32-bit SRAM */
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static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int index)
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{
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efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Read from a dword register forming part of a table */
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/* Read a 32-bit CSR forming part of a table, or 32-bit SRAM */
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static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int index)
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{
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@ -231,25 +230,26 @@ static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
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#define EFX_PAGED_REG(page, reg) \
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((page) * EFX_PAGE_BLOCK_SIZE + (reg))
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/* As for efx_writeo(), but for a page-mapped register. */
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/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
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static inline void efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int page)
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{
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efx_writeo(efx, value, EFX_PAGED_REG(page, reg));
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}
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/* As for efx_writed(), but for a page-mapped register. */
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/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
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* RX_DESC_UPD or TX_DESC_UPD)
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*/
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static inline void efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int page)
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{
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efx_writed(efx, value, EFX_PAGED_REG(page, reg));
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}
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/* Write dword to page-mapped register with an extra lock.
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*
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* As for efx_writed_page(), but for a register that suffers from
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* SFC bug 3181. Take out a lock so the BIU collector cannot be
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* confused. */
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/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
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* in the BIU means that writes to TIMER_COMMAND[0] invalidate the
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* collector register.
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*/
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static inline void efx_writed_page_locked(struct efx_nic *efx,
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efx_dword_t *value,
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unsigned int reg,
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