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Staging: rtl8192u: r8192U.h - style fix 

Fixed style of block comments
Found using checkpatch

Signed-off-by: Derek Robson <robsonde@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Derek Robson 2017-02-16 18:32:01 +13:00 committed by Greg Kroah-Hartman
parent 8ec5252530
commit 9e664c6fea
1 changed files with 26 additions and 13 deletions
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39
drivers/staging/rtl8192u/r8192U.h
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@ -626,7 +626,8 @@ typedef struct Stats {
long signal_quality;
long last_signal_strength_inpercent;
/* Correct smoothed ss in dbm, only used in driver
* to report real power now */
* to report real power now
*/
long recv_signal_power;
u8 rx_rssi_percentage[4];
u8 rx_evm_percentage[2];
@ -672,32 +673,40 @@ typedef struct _BB_REGISTER_DEFINITION {
/* Tx gain stage: 0x80c~0x80f [4 bytes] */
u32 rfTxGainStage;
/* wire parameter control1: 0x820~0x823, 0x828~0x82b,
* 0x830~0x833, 0x838~0x83b [16 bytes] */
* 0x830~0x833, 0x838~0x83b [16 bytes]
*/
u32 rfHSSIPara1;
/* wire parameter control2: 0x824~0x827, 0x82c~0x82f,
* 0x834~0x837, 0x83c~0x83f [16 bytes] */
* 0x834~0x837, 0x83c~0x83f [16 bytes]
*/
u32 rfHSSIPara2;
/* Tx Rx antenna control: 0x858~0x85f [16 bytes] */
u32 rfSwitchControl;
/* AGC parameter control1: 0xc50~0xc53, 0xc58~0xc5b,
* 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
* 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
*/
u32 rfAGCControl1;
/* AGC parameter control2: 0xc54~0xc57, 0xc5c~0xc5f,
* 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
* 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
*/
u32 rfAGCControl2;
/* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
* 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
* 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
*/
u32 rfRxIQImbalance;
/* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
* 0xc10~0xc13, 0xc18~0xc1b,
* 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
* 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
*/
u32 rfRxAFE;
/* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
* 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
* 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
*/
u32 rfTxIQImbalance;
/* Tx IQ DC Offset and Tx DFIR type:
* 0xc84~0xc87, 0xc8c~0xc8f,
* 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
* 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
*/
u32 rfTxAFE;
/* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBack;
@ -776,7 +785,8 @@ typedef struct _phy_ofdm_rx_status_report_819xusb {
typedef struct _phy_cck_rx_status_report_819xusb {
/* For CCK rate descriptor. This is an unsigned 8:1 variable.
* LSB bit presend 0.5. And MSB 7 bts presend a signed value.
* Range from -64~+63.5. */
* Range from -64~+63.5.
*/
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
@ -991,7 +1001,8 @@ typedef struct r8192_priv {
/* Control channel sub-carrier */
u8 nCur40MhzPrimeSC;
/* Test for shorten RF configuration time.
* We save RF reg0 in this variable to reduce RF reading. */
* We save RF reg0 in this variable to reduce RF reading.
*/
u32 RfReg0Value[4];
u8 NumTotalRFPath;
bool brfpath_rxenable[4];
@ -1009,11 +1020,13 @@ typedef struct r8192_priv {
bool bstore_last_dtpflag;
/* Define to discriminate on High power State or
* on sitesurvey to change Tx gain index */
* on sitesurvey to change Tx gain index
*/
bool bstart_txctrl_bydtp;
rate_adaptive rate_adaptive;
/* TX power tracking
* OPEN/CLOSE TX POWER TRACKING */
* OPEN/CLOSE TX POWER TRACKING
*/
txbbgain_struct txbbgain_table[TxBBGainTableLength];
u8 txpower_count; /* For 6 sec do tracking again */
bool btxpower_trackingInit;