KVM: Improve local apic timer wraparound handling
Better handle wrap-around cases when reading the APIC CCR (current count register). Also, if ICR is 0, CCR should also be 0... previously reading CCR before setting ICR would result in a large kinda-random number. Signed-off-by: Kevin Pedretti <kevin.pedretti@gmail.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
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@ -494,12 +494,19 @@ static void apic_send_ipi(struct kvm_lapic *apic)
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static u32 apic_get_tmcct(struct kvm_lapic *apic)
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{
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u32 counter_passed;
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ktime_t passed, now = apic->timer.dev.base->get_time();
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u32 tmcct = apic_get_reg(apic, APIC_TMICT);
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u64 counter_passed;
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ktime_t passed, now;
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u32 tmcct;
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ASSERT(apic != NULL);
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now = apic->timer.dev.base->get_time();
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tmcct = apic_get_reg(apic, APIC_TMICT);
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/* if initial count is 0, current count should also be 0 */
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if (tmcct == 0)
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return 0;
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if (unlikely(ktime_to_ns(now) <=
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ktime_to_ns(apic->timer.last_update))) {
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/* Wrap around */
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@ -514,15 +521,24 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
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counter_passed = div64_64(ktime_to_ns(passed),
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(APIC_BUS_CYCLE_NS * apic->timer.divide_count));
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tmcct -= counter_passed;
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if (tmcct <= 0) {
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if (unlikely(!apic_lvtt_period(apic)))
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if (counter_passed > tmcct) {
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if (unlikely(!apic_lvtt_period(apic))) {
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/* one-shot timers stick at 0 until reset */
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tmcct = 0;
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else
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do {
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tmcct += apic_get_reg(apic, APIC_TMICT);
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} while (tmcct <= 0);
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} else {
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/*
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* periodic timers reset to APIC_TMICT when they
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* hit 0. The while loop simulates this happening N
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* times. (counter_passed %= tmcct) would also work,
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* but might be slower or not work on 32-bit??
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*/
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while (counter_passed > tmcct)
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counter_passed -= tmcct;
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tmcct -= counter_passed;
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}
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} else {
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tmcct -= counter_passed;
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}
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return tmcct;
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