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powerpc/perf: Update Power PMU cache_events to u64 type 

Events of type PERF_TYPE_HW_CACHE was described for Power PMU
as: int (*cache_events)[type][op][result];

where type, op, result values unpacked from the event attribute config
value is used to generate the raw event code at runtime.

So far the event code values which used to create these cache-related
events were within 32 bit and `int` type worked. In power10,
some of the event codes are of 64-bit value and hence update the
Power PMU cache_events to `u64` type in `power_pmu` struct.
Also propagate this change to existing all PMU driver code paths
which are using ppmu->cache_events.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-4-git-send-email-atrajeev@linux.vnet.ibm.com
This commit is contained in:
Athira Rajeev 2020-07-17 10:38:15 -04:00 committed by Michael Ellerman
parent 7e4a145e5b
commit 9d4fc86dcd
11 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/include/asm/perf_event_server.h
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@ -53,7 +53,7 @@ struct power_pmu {
const struct attribute_group **attr_groups; const struct attribute_group **attr_groups;
int n_generic; int n_generic;
int *generic_events; int *generic_events;
int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] u64 (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX]; [PERF_COUNT_HW_CACHE_RESULT_MAX];

2
arch/powerpc/perf/core-book3s.c
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@ -1790,7 +1790,7 @@ static void hw_perf_event_destroy(struct perf_event *event)
static int hw_perf_cache_event(u64 config, u64 *eventp) static int hw_perf_cache_event(u64 config, u64 *eventp)
{ {
unsigned long type, op, result; unsigned long type, op, result;
int ev; u64 ev;
if (!ppmu->cache_events) if (!ppmu->cache_events)
return -EINVAL; return -EINVAL;

2
arch/powerpc/perf/generic-compat-pmu.c
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@ -101,7 +101,7 @@ static int compat_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[ C(L1D) ] = { [ C(L1D) ] = {
[ C(OP_READ) ] = { [ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0, [ C(RESULT_ACCESS) ] = 0,

2
arch/powerpc/perf/mpc7450-pmu.c
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@ -361,7 +361,7 @@ static int mpc7450_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0x225 }, [C(OP_READ)] = { 0, 0x225 },
[C(OP_WRITE)] = { 0, 0x227 }, [C(OP_WRITE)] = { 0, 0x227 },

2
arch/powerpc/perf/power5+-pmu.c
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@ -619,7 +619,7 @@ static int power5p_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x1c10a8, 0x3c1088 }, [C(OP_READ)] = { 0x1c10a8, 0x3c1088 },
[C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 }, [C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 },

2
arch/powerpc/perf/power5-pmu.c
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@ -561,7 +561,7 @@ static int power5_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x4c1090, 0x3c1088 }, [C(OP_READ)] = { 0x4c1090, 0x3c1088 },
[C(OP_WRITE)] = { 0x3c1090, 0xc10c3 }, [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },

2
arch/powerpc/perf/power6-pmu.c
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@ -481,7 +481,7 @@ static int power6_generic_events[] = {
* are event codes. * are event codes.
* The "DTLB" and "ITLB" events relate to the DERAT and IERAT. * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
*/ */
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x280030, 0x80080 }, [C(OP_READ)] = { 0x280030, 0x80080 },
[C(OP_WRITE)] = { 0x180032, 0x80088 }, [C(OP_WRITE)] = { 0x180032, 0x80088 },

2
arch/powerpc/perf/power7-pmu.c
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@ -333,7 +333,7 @@ static int power7_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0xc880, 0x400f0 }, [C(OP_READ)] = { 0xc880, 0x400f0 },
[C(OP_WRITE)] = { 0, 0x300f0 }, [C(OP_WRITE)] = { 0, 0x300f0 },

2
arch/powerpc/perf/power8-pmu.c
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@ -253,7 +253,7 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[ C(L1D) ] = { [ C(L1D) ] = {
[ C(OP_READ) ] = { [ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1, [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,

2
arch/powerpc/perf/power9-pmu.c
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@ -310,7 +310,7 @@ static void power9_config_bhrb(u64 pmu_bhrb_filter)
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[ C(L1D) ] = { [ C(L1D) ] = {
[ C(OP_READ) ] = { [ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1, [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,

2
arch/powerpc/perf/ppc970-pmu.c
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@ -432,7 +432,7 @@ static int ppc970_generic_events[] = {
* 0 means not supported, -1 means nonsensical, other values * 0 means not supported, -1 means nonsensical, other values
* are event codes. * are event codes.
*/ */
static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x8810, 0x3810 }, [C(OP_READ)] = { 0x8810, 0x3810 },
[C(OP_WRITE)] = { 0x7810, 0x813 }, [C(OP_WRITE)] = { 0x7810, 0x813 },