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amd64_edac: Fix logic to determine channel for F15 M30h processors 

Update current channel selection logic to include F15h, M30h memory
controllers.

Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
(Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/1390338216-3873-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Aravind Gopalakrishnan 2014-01-21 15:03:36 -06:00 committed by Borislav Petkov
parent e245e3b25f
commit 9d0e8d8348
1 changed files with 11 additions and 3 deletions
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14
drivers/edac/amd64_edac.c
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@ -1239,9 +1239,17 @@ static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
if (num_dcts_intlv == 2) {
select = (sys_addr >> 8) & 0x3;
channel = select ? 0x3 : 0;
} else if (num_dcts_intlv == 4)
channel = (sys_addr >> 8) & 0x7;
} else if (num_dcts_intlv == 4) {
u8 intlv_addr = dct_sel_interleave_addr(pvt);
switch (intlv_addr) {
case 0x4:
channel = (sys_addr >> 8) & 0x3;
break;
case 0x5:
channel = (sys_addr >> 9) & 0x3;
break;
}
}
return channel;
}