ARM: OMAP2+: Drop legacy struct omap_hwmod_addr_space
With all of mach-omap2 booting now in device tree only mode, we can get the module IO range from device tree and just drop the legacy hwmod struct omap_hwmod_addr_space. Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
c2b84a9bb3
commit
9cffb1a050
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@ -198,15 +198,12 @@ obj-y += omap_hwmod_common_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
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obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o
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@ -1101,82 +1101,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
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oh->prcm.omap4.clkctrl_offs, 0);
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}
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/**
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* _count_ocp_if_addr_spaces - count the number of address space entries for @oh
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* @oh: struct omap_hwmod *oh
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*
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* Count and return the number of address space ranges associated with
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* the hwmod @oh. Used to allocate struct resource data. Returns 0
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* if @oh is NULL.
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*/
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static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
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{
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struct omap_hwmod_addr_space *mem;
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int i = 0;
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if (!os || !os->addr)
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return 0;
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do {
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mem = &os->addr[i++];
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} while (mem->pa_start != mem->pa_end);
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return i-1;
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}
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/**
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* _get_addr_space_by_name - fetch address space start & end by name
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* @oh: struct omap_hwmod * to operate on
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* @name: pointer to the name of the address space to fetch (optional)
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* @pa_start: pointer to a u32 to store the starting address to
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* @pa_end: pointer to a u32 to store the ending address to
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*
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* Retrieve address space start and end addresses for the IP block
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* pointed to by @oh. The data will be filled into the addresses
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* pointed to by @pa_start and @pa_end. When @name is non-null, the
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* address space data associated with the named entry will be
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* returned. If @name is null, the first matching entry will be
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* returned. Data order is not meaningful in hwmod data, so callers
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* are strongly encouraged to use a non-null @name whenever possible
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* to avoid unpredictable effects if hwmod data is later added that
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* causes data ordering to change. Returns 0 upon success or a
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* negative error code upon error.
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*/
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static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
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u32 *pa_start, u32 *pa_end)
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{
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int j;
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struct omap_hwmod_ocp_if *os;
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bool found = false;
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list_for_each_entry(os, &oh->slave_ports, node) {
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if (!os->addr)
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return -ENOENT;
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j = 0;
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while (os->addr[j].pa_start != os->addr[j].pa_end) {
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if (name == os->addr[j].name ||
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!strcmp(name, os->addr[j].name)) {
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found = true;
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break;
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}
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j++;
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}
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if (found)
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break;
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}
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if (!found)
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return -ENOENT;
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*pa_start = os->addr[j].pa_start;
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*pa_end = os->addr[j].pa_end;
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return 0;
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}
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/**
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* _save_mpu_port_index - find and save the index to @oh's MPU port
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* @oh: struct omap_hwmod *
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@ -1227,32 +1151,6 @@ static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
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return oh->_mpu_port;
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};
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/**
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* _find_mpu_rt_addr_space - return MPU register target address space for @oh
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* @oh: struct omap_hwmod *
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*
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* Returns a pointer to the struct omap_hwmod_addr_space record representing
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* the register target MPU address space; or returns NULL upon error.
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*/
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static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
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{
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struct omap_hwmod_ocp_if *os;
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struct omap_hwmod_addr_space *mem;
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int found = 0, i = 0;
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os = _find_mpu_rt_port(oh);
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if (!os || !os->addr)
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return NULL;
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do {
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mem = &os->addr[i++];
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if (mem->flags & ADDR_TYPE_RT)
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found = 1;
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} while (!found && mem->pa_start != mem->pa_end);
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return (found) ? mem : NULL;
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}
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/**
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* _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
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* @oh: struct omap_hwmod *
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@ -2349,7 +2247,6 @@ int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
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static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
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int index, struct device_node *np)
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{
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struct omap_hwmod_addr_space *mem;
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void __iomem *va_start = NULL;
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struct resource res;
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int error;
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@ -2367,35 +2264,22 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
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if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
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return -ENXIO;
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mem = _find_mpu_rt_addr_space(oh);
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if (!mem) {
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pr_debug("omap_hwmod: %s: no MPU register target found\n",
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oh->name);
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/* Extract the IO space from device tree blob */
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if (!np) {
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pr_err("omap_hwmod: %s: no dt node\n", oh->name);
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return -ENXIO;
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}
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/* Do we have a dts range for the interconnect target module? */
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error = omap_hwmod_parse_module_range(oh, np, &res);
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if (!error)
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va_start = ioremap(res.start, resource_size(&res));
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/* No ranges, rely on device reg entry */
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if (!va_start)
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va_start = of_iomap(np, index + oh->mpu_rt_idx);
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} else {
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va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
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if (!np) {
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pr_err("omap_hwmod: %s: no dt node\n", oh->name);
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return -ENXIO;
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}
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/* Do we have a dts range for the interconnect target module? */
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error = omap_hwmod_parse_module_range(oh, np, &res);
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if (!error)
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va_start = ioremap(res.start, resource_size(&res));
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/* No ranges, rely on device reg entry */
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if (!va_start)
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va_start = of_iomap(np, index + oh->mpu_rt_idx);
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if (!va_start) {
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if (mem)
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pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
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else
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pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n",
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oh->name, index, np);
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pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n",
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oh->name, index, np);
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return -ENXIO;
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}
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@ -3299,117 +3183,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
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* IP block data retrieval functions
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*/
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/**
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* omap_hwmod_count_resources - count number of struct resources needed by hwmod
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* @oh: struct omap_hwmod *
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* @flags: Type of resources to include when counting (IRQ/DMA/MEM)
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*
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* Count the number of struct resource array elements necessary to
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* contain omap_hwmod @oh resources. Intended to be called by code
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* that registers omap_devices. Intended to be used to determine the
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* size of a dynamically-allocated struct resource array, before
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* calling omap_hwmod_fill_resources(). Returns the number of struct
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* resource array elements needed.
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*
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* XXX This code is not optimized. It could attempt to merge adjacent
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* resource IDs.
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*
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*/
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int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags)
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{
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int ret = 0;
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if (flags & IORESOURCE_MEM) {
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struct omap_hwmod_ocp_if *os;
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list_for_each_entry(os, &oh->slave_ports, node)
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ret += _count_ocp_if_addr_spaces(os);
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}
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return ret;
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}
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/**
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* omap_hwmod_fill_resources - fill struct resource array with hwmod data
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* @oh: struct omap_hwmod *
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* @res: pointer to the first element of an array of struct resource to fill
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*
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* Fill the struct resource array @res with resource data from the
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* omap_hwmod @oh. Intended to be called by code that registers
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* omap_devices. See also omap_hwmod_count_resources(). Returns the
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* number of array elements filled.
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*/
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int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
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{
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struct omap_hwmod_ocp_if *os;
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int j, addr_cnt;
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int r = 0;
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/* For each memory area, fill in array.*/
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list_for_each_entry(os, &oh->slave_ports, node) {
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addr_cnt = _count_ocp_if_addr_spaces(os);
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for (j = 0; j < addr_cnt; j++) {
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(res + r)->name = (os->addr + j)->name;
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(res + r)->start = (os->addr + j)->pa_start;
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(res + r)->end = (os->addr + j)->pa_end;
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(res + r)->flags = IORESOURCE_MEM;
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r++;
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}
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}
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return r;
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}
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/**
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* omap_hwmod_get_resource_byname - fetch IP block integration data by name
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* @oh: struct omap_hwmod * to operate on
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* @type: one of the IORESOURCE_* constants from include/linux/ioport.h
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* @name: pointer to the name of the data to fetch (optional)
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* @rsrc: pointer to a struct resource, allocated by the caller
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*
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* Retrieve MPU IRQ, SDMA request line, or address space start/end
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* data for the IP block pointed to by @oh. The data will be filled
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* into a struct resource record pointed to by @rsrc. The struct
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* resource must be allocated by the caller. When @name is non-null,
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* the data associated with the matching entry in the IRQ/SDMA/address
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* space hwmod data arrays will be returned. If @name is null, the
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* first array entry will be returned. Data order is not meaningful
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* in hwmod data, so callers are strongly encouraged to use a non-null
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* @name whenever possible to avoid unpredictable effects if hwmod
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* data is later added that causes data ordering to change. This
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* function is only intended for use by OMAP core code. Device
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* drivers should not call this function - the appropriate bus-related
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* data accessor functions should be used instead. Returns 0 upon
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* success or a negative error code upon error.
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*/
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int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
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const char *name, struct resource *rsrc)
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{
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int r;
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u32 pa_start, pa_end;
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if (!oh || !rsrc)
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return -EINVAL;
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if (type == IORESOURCE_MEM) {
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r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
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if (r)
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return r;
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rsrc->start = pa_start;
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rsrc->end = pa_end;
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} else {
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return -EINVAL;
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}
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rsrc->flags = type;
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rsrc->name = name;
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return 0;
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}
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/**
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* omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
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* @oh: struct omap_hwmod *
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@ -198,34 +198,6 @@ struct omap_hwmod_omap2_firewall {
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u8 flags;
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};
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/*
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* omap_hwmod_addr_space.flags bits
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*
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* ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
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* ADDR_TYPE_RT: Address space contains module register target data.
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*/
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#define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */
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#define ADDR_TYPE_RT (1 << 1)
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/**
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* struct omap_hwmod_addr_space - address space handled by the hwmod
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* @name: name of the address space
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* @pa_start: starting physical address
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* @pa_end: ending physical address
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* @flags: (see omap_hwmod_addr_space.flags macros above)
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*
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* Address space doesn't necessarily follow physical interconnect
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* structure. GPMC is one example.
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*/
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struct omap_hwmod_addr_space {
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const char *name;
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u32 pa_start;
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u32 pa_end;
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u8 flags;
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};
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/*
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* omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
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* interface to interact with the hwmod. Used to add sleep dependencies
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@ -370,7 +370,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_dma_system_hwmod,
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.clk = "sdma_ick",
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.addr = omap2_dma_system_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -571,7 +571,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2430_dma_system_hwmod,
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.clk = "sdma_ick",
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.addr = omap2_dma_system_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -1,27 +0,0 @@
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/*
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* omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
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*
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* Copyright (C) 2009-2011 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX handle crossbar/shared link difference for L3?
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <asm/sizes.h>
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
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{
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.pa_start = 0x48056000,
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.pa_end = 0x48056000 + SZ_4K - 1,
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.flags = ADDR_TYPE_RT,
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},
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{ },
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};
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@ -159,54 +159,24 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
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{
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.pa_start = 0x48300000,
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.pa_end = 0x48300000 + SZ_16 - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_epwmss0_hwmod,
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.clk = "l4ls_gclk",
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.addr = am33xx_epwmss0_addr_space,
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
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{
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.pa_start = 0x48302000,
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.pa_end = 0x48302000 + SZ_16 - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_epwmss1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.addr = am33xx_epwmss1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48304000,
|
||||
.pa_end = 0x48304000 + SZ_16 - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am33xx_epwmss2_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.addr = am33xx_epwmss2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -250,38 +220,18 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
|
|||
};
|
||||
|
||||
/* l4 ls -> mcasp0 */
|
||||
static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48038000,
|
||||
.pa_end = 0x48038000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am33xx_mcasp0_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.addr = am33xx_mcasp0_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4 ls -> mcasp1 */
|
||||
static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4803C000,
|
||||
.pa_end = 0x4803C000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am33xx_mcasp1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.addr = am33xx_mcasp1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -382,56 +332,26 @@ struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
|
|||
};
|
||||
|
||||
/* l3 main -> tpcc0 */
|
||||
static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49800000,
|
||||
.pa_end = 0x49800000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_tptc0_hwmod,
|
||||
.clk = "l3_gclk",
|
||||
.addr = am33xx_tptc0_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3 main -> tpcc1 */
|
||||
static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49900000,
|
||||
.pa_end = 0x49900000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_tptc1_hwmod,
|
||||
.clk = "l3_gclk",
|
||||
.addr = am33xx_tptc1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3 main -> tpcc2 */
|
||||
static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49a00000,
|
||||
.pa_end = 0x49a00000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_tptc2_hwmod,
|
||||
.clk = "l3_gclk",
|
||||
.addr = am33xx_tptc2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -483,38 +403,18 @@ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
|
|||
};
|
||||
|
||||
/* l3 main -> sha0 HIB2 */
|
||||
static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x53100000,
|
||||
.pa_end = 0x53100000 + SZ_512 - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_sha0_hwmod,
|
||||
.clk = "sha0_fck",
|
||||
.addr = am33xx_sha0_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3 main -> AES0 HIB2 */
|
||||
static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x53500000,
|
||||
.pa_end = 0x53500000 + SZ_1M - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_aes0_hwmod,
|
||||
.clk = "aes0_fck",
|
||||
.addr = am33xx_aes0_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -320,20 +320,11 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
|
|||
* Interfaces
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4c000000,
|
||||
.pa_end = 0x4c000fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
/* l3 main -> emif */
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_emif_hwmod,
|
||||
.clk = "dpll_core_m4_ck",
|
||||
.addr = am33xx_emif_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -370,20 +361,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
|
|||
};
|
||||
|
||||
/* l3_main -> debugss */
|
||||
static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4b000000,
|
||||
.pa_end = 0x4b000000 + SZ_16M - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_debugss_hwmod,
|
||||
.clk = "dpll_core_m4_ck",
|
||||
.addr = am33xx_debugss_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -428,20 +409,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
|
|||
};
|
||||
|
||||
/* L4 WKUP -> ADC_TSC */
|
||||
static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x44E0D000,
|
||||
.pa_end = 0x44E0D000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
|
||||
.master = &am33xx_l4_wkup_hwmod,
|
||||
.slave = &am33xx_adc_tsc_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.addr = am33xx_adc_tsc_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -452,20 +423,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4830E000,
|
||||
.pa_end = 0x4830E000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_lcdc_hwmod,
|
||||
.clk = "dpll_core_m4_ck",
|
||||
.addr = am33xx_lcdc_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2098,20 +2098,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
|
|||
};
|
||||
|
||||
/* L4 CORE -> SR1 interface */
|
||||
static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP34XX_SR1_BASE,
|
||||
.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_sr1_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -2119,25 +2109,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
|
|||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap36xx_sr1_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* L4 CORE -> SR1 interface */
|
||||
static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP34XX_SR2_BASE,
|
||||
.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
/* L4 CORE -> SR2 interface */
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_sr2_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -2145,7 +2125,6 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
|
|||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap36xx_sr2_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -2514,21 +2493,11 @@ static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dma_system_hwmod,
|
||||
.clk = "core_l4_ick",
|
||||
.addr = omap3xxx_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3392,81 +3392,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
|
||||
{
|
||||
.name = "dmem",
|
||||
.pa_start = 0x40180000,
|
||||
.pa_end = 0x4018ffff
|
||||
},
|
||||
{
|
||||
.name = "cmem",
|
||||
.pa_start = 0x401a0000,
|
||||
.pa_end = 0x401a1fff
|
||||
},
|
||||
{
|
||||
.name = "smem",
|
||||
.pa_start = 0x401c0000,
|
||||
.pa_end = 0x401c5fff
|
||||
},
|
||||
{
|
||||
.name = "pmem",
|
||||
.pa_start = 0x401e0000,
|
||||
.pa_end = 0x401e1fff
|
||||
},
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x401f1000,
|
||||
.pa_end = 0x401f13ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> aess */
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_aess_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_aess_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
|
||||
{
|
||||
.name = "dmem_dma",
|
||||
.pa_start = 0x49080000,
|
||||
.pa_end = 0x4908ffff
|
||||
},
|
||||
{
|
||||
.name = "cmem_dma",
|
||||
.pa_start = 0x490a0000,
|
||||
.pa_end = 0x490a1fff
|
||||
},
|
||||
{
|
||||
.name = "smem_dma",
|
||||
.pa_start = 0x490c0000,
|
||||
.pa_end = 0x490c5fff
|
||||
},
|
||||
{
|
||||
.name = "pmem_dma",
|
||||
.pa_start = 0x490e0000,
|
||||
.pa_end = 0x490e1fff
|
||||
},
|
||||
{
|
||||
.name = "dma",
|
||||
.pa_start = 0x490f1000,
|
||||
.pa_end = 0x490f13ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> aess (dma) */
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_aess_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_aess_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3486,75 +3424,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a002000,
|
||||
.pa_end = 0x4a0027ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> ctrl_module_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_ctrl_module_core_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a100000,
|
||||
.pa_end = 0x4a1007ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> ctrl_module_pad_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_pad_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_ctrl_module_pad_core_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a30c000,
|
||||
.pa_end = 0x4a30c7ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_wkup -> ctrl_module_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_wkup_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.addr = omap44xx_ctrl_module_wkup_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a31e000,
|
||||
.pa_end = 0x4a31e7ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_wkup -> ctrl_module_pad_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.addr = omap44xx_ctrl_module_pad_wkup_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3566,21 +3464,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a056000,
|
||||
.pa_end = 0x4a056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_dma_system_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3616,255 +3504,115 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58000000,
|
||||
.pa_end = 0x5800007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48040000,
|
||||
.pa_end = 0x4804007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58001000,
|
||||
.pa_end = 0x58001fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_dispc_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_dispc_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48041000,
|
||||
.pa_end = 0x48041fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_dispc_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_dispc_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58004000,
|
||||
.pa_end = 0x580041ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_dsi1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_dsi1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_dsi1_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48044000,
|
||||
.pa_end = 0x480441ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_dsi1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_dsi1_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_dsi1_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58005000,
|
||||
.pa_end = 0x580051ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_dsi2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_dsi2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_dsi2_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48045000,
|
||||
.pa_end = 0x480451ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_dsi2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_dsi2_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_dsi2_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58006000,
|
||||
.pa_end = 0x58006fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_hdmi */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_hdmi_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_hdmi_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48046000,
|
||||
.pa_end = 0x48046fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_hdmi */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_hdmi_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_hdmi_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58002000,
|
||||
.pa_end = 0x580020ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_rfbi */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_rfbi_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_rfbi_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48042000,
|
||||
.pa_end = 0x480420ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_rfbi */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_rfbi_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_rfbi_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x58003000,
|
||||
.pa_end = 0x580030ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> dss_venc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_dss_venc_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_dss_venc_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48043000,
|
||||
.pa_end = 0x480430ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> dss_venc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_dss_venc_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dss_venc_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -3884,21 +3632,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a10a000,
|
||||
.pa_end = 0x4a10a1ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> fdif */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_fdif_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_fdif_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3958,57 +3696,27 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x56000000,
|
||||
.pa_end = 0x5600ffff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> gpu */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_gpu_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_gpu_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x480b2000,
|
||||
.pa_end = 0x480b201f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> hdq1w */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_hdq1w_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_hdq1w_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a058000,
|
||||
.pa_end = 0x4a05bfff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> hsi */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_hsi_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_hsi_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -4052,21 +3760,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x52000000,
|
||||
.pa_end = 0x520000ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> iss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_iss_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_iss_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -4102,39 +3800,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x40128000,
|
||||
.pa_end = 0x401283ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> mcasp */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_mcasp_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_mcasp_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x49028000,
|
||||
.pa_end = 0x490283ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> mcasp (dma) */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_mcasp_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_mcasp_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -4314,111 +3992,51 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4012c000,
|
||||
.pa_end = 0x4012c3ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> slimbus1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_slimbus1_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_slimbus1_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4902c000,
|
||||
.pa_end = 0x4902c3ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> slimbus1 (dma) */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_slimbus1_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_slimbus1_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48076000,
|
||||
.pa_end = 0x480763ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> slimbus2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_slimbus2_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_slimbus2_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a0dd000,
|
||||
.pa_end = 0x4a0dd03f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> smartreflex_core */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_smartreflex_core_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_smartreflex_core_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a0db000,
|
||||
.pa_end = 0x4a0db03f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> smartreflex_iva */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_smartreflex_iva_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_smartreflex_iva_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a0d9000,
|
||||
.pa_end = 0x4a0d903f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> smartreflex_mpu */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_smartreflex_mpu_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_smartreflex_mpu_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -4590,39 +4208,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x40130000,
|
||||
.pa_end = 0x4013007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> wd_timer3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_wd_timer3_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_wd_timer3_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x49030000,
|
||||
.pa_end = 0x4903007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_abe -> wd_timer3 (dma) */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_wd_timer3_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_wd_timer3_dma_addrs,
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2245,21 +2245,11 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a056000,
|
||||
.pa_end = 0x4a056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
|
||||
.master = &omap54xx_l4_cfg_hwmod,
|
||||
.slave = &omap54xx_dma_system_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.addr = omap54xx_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2988,21 +2988,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a056000,
|
||||
.pa_end = 0x4a056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_dma_system_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3246,21 +3236,11 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x480b2000,
|
||||
.pa_end = 0x480b201f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per1 -> hdq1w */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
|
||||
.master = &dra7xx_l4_per1_hwmod,
|
||||
.slave = &dra7xx_hdq1w_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_hdq1w_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -3544,58 +3524,27 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
|
||||
{
|
||||
.name = "sysc",
|
||||
.pa_start = 0x4a141100,
|
||||
.pa_end = 0x4a141107,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> sata */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_sata_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.addr = dra7xx_sata_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a0dd000,
|
||||
.pa_end = 0x4a0dd07f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> smartreflex_core */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_smartreflex_core_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.addr = dra7xx_smartreflex_core_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a0d9000,
|
||||
.pa_end = 0x4a0d907f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> smartreflex_mpu */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
.slave = &dra7xx_smartreflex_mpu_hwmod,
|
||||
.clk = "l4_root_clk_div",
|
||||
.addr = dra7xx_smartreflex_mpu_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1260,15 +1260,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49800000,
|
||||
.pa_end = 0x49800000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
|
||||
.name = "tptc0",
|
||||
};
|
||||
|
|
@ -1290,7 +1281,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
|
|||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc0_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc0_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -1298,19 +1288,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
|
|||
.master = &dm81xx_tptc0_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc0_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49900000,
|
||||
.pa_end = 0x49900000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
|
||||
.name = "tptc1",
|
||||
};
|
||||
|
|
@ -1332,7 +1312,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
|
|||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc1_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -1340,19 +1319,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
|
|||
.master = &dm81xx_tptc1_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49a00000,
|
||||
.pa_end = 0x49a00000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
|
||||
.name = "tptc2",
|
||||
};
|
||||
|
|
@ -1374,7 +1343,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
|
|||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc2_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -1382,19 +1350,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
|
|||
.master = &dm81xx_tptc2_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x49b00000,
|
||||
.pa_end = 0x49b00000 + SZ_8K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
|
||||
.name = "tptc3",
|
||||
};
|
||||
|
|
@ -1416,7 +1374,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
|
|||
.master = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.slave = &dm81xx_tptc3_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc3_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -1424,7 +1381,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
|
|||
.master = &dm81xx_tptc3_hwmod,
|
||||
.slave = &dm81xx_alwon_l3_fast_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.addr = dm81xx_tptc3_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,9 +18,6 @@
|
|||
#include "common.h"
|
||||
#include "display.h"
|
||||
|
||||
/* Common address space across OMAP2xxx/3xxx */
|
||||
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
|
||||
|
||||
/* Common IP block data across OMAP2xxx */
|
||||
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
|
||||
extern struct omap_hwmod omap2xxx_l3_main_hwmod;
|
||||
|
|
@ -89,9 +86,6 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
|
|||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
|
||||
|
||||
/* Common IP block data across OMAP2/3 */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
|
||||
/* OMAP hwmod classes - forward declarations */
|
||||
extern struct omap_hwmod_class l3_hwmod_class;
|
||||
extern struct omap_hwmod_class l4_hwmod_class;
|
||||
|
|
|
|||
Loading…
Reference in New Issue