Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next
more misc amdgpu fixes. * 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: fix rmmod KCQ disable failed error drm/amdgpu: fix kernel hang when starting VNC server drm/amdgpu: don't skip attributes when powerplay is enabled drm/amd/pp: fix typecast error in powerplay. Revert "drm/radeon: dont switch vt on suspend" drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence drm/amd/powerplay: fix unfreeze level smc message for smu7 drm/amdgpu:fix memleak drm/amdgpu:fix memleak in takedown
This commit is contained in:
commit
9cae7751dc
|
@ -1498,7 +1498,7 @@ out:
|
|||
wait->out.status = (r > 0);
|
||||
wait->out.first_signaled = first;
|
||||
|
||||
if (array[first])
|
||||
if (first < fence_count && array[first])
|
||||
r = array[first]->error;
|
||||
else
|
||||
r = 0;
|
||||
|
|
|
@ -1836,6 +1836,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
|
|||
adev->ip_blocks[i].status.hw = false;
|
||||
}
|
||||
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
|
||||
amdgpu_ucode_fini_bo(adev);
|
||||
|
||||
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
|
||||
if (!adev->ip_blocks[i].status.sw)
|
||||
continue;
|
||||
|
|
|
@ -328,7 +328,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
|
|||
r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
|
||||
bo->tbo.ttm->pages);
|
||||
if (r)
|
||||
goto unlock_mmap_sem;
|
||||
goto release_object;
|
||||
|
||||
r = amdgpu_bo_reserve(bo, true);
|
||||
if (r)
|
||||
|
@ -353,9 +353,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
|
|||
free_pages:
|
||||
release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
|
||||
|
||||
unlock_mmap_sem:
|
||||
up_read(¤t->mm->mmap_sem);
|
||||
|
||||
release_object:
|
||||
drm_gem_object_put_unlocked(gobj);
|
||||
|
||||
|
|
|
@ -71,12 +71,6 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
|
|||
{
|
||||
struct amdgpu_gtt_mgr *mgr = man->priv;
|
||||
|
||||
spin_lock(&mgr->lock);
|
||||
if (!drm_mm_clean(&mgr->mm)) {
|
||||
spin_unlock(&mgr->lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
drm_mm_takedown(&mgr->mm);
|
||||
spin_unlock(&mgr->lock);
|
||||
kfree(mgr);
|
||||
|
|
|
@ -946,6 +946,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
|
|||
struct amdgpu_device *adev = dev_get_drvdata(dev);
|
||||
umode_t effective_mode = attr->mode;
|
||||
|
||||
/* no skipping for powerplay */
|
||||
if (adev->powerplay.cgs_device)
|
||||
return effective_mode;
|
||||
|
||||
/* Skip limit attributes if DPM is not enabled */
|
||||
if (!adev->pm.dpm_enabled &&
|
||||
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
|
||||
|
|
|
@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle)
|
|||
ret = adev->powerplay.ip_funcs->hw_fini(
|
||||
adev->powerplay.pp_handle);
|
||||
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
|
||||
amdgpu_ucode_fini_bo(adev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -442,8 +442,6 @@ static int psp_hw_fini(void *handle)
|
|||
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
||||
return 0;
|
||||
|
||||
amdgpu_ucode_fini_bo(adev);
|
||||
|
||||
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
|
||||
|
||||
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
|
||||
|
|
|
@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man)
|
|||
struct amdgpu_vram_mgr *mgr = man->priv;
|
||||
|
||||
spin_lock(&mgr->lock);
|
||||
if (!drm_mm_clean(&mgr->mm)) {
|
||||
spin_unlock(&mgr->lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
drm_mm_takedown(&mgr->mm);
|
||||
spin_unlock(&mgr->lock);
|
||||
kfree(mgr);
|
||||
|
|
|
@ -4670,6 +4670,14 @@ static int gfx_v7_0_sw_fini(void *handle)
|
|||
gfx_v7_0_cp_compute_fini(adev);
|
||||
gfx_v7_0_rlc_fini(adev);
|
||||
gfx_v7_0_mec_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if (adev->gfx.rlc.cp_table_size) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v7_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -2118,6 +2118,15 @@ static int gfx_v8_0_sw_fini(void *handle)
|
|||
|
||||
gfx_v8_0_mec_fini(adev);
|
||||
gfx_v8_0_rlc_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if ((adev->asic_type == CHIP_CARRIZO) ||
|
||||
(adev->asic_type == CHIP_STONEY)) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v8_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -1468,6 +1468,14 @@ static int gfx_v9_0_sw_fini(void *handle)
|
|||
|
||||
gfx_v9_0_mec_fini(adev);
|
||||
gfx_v9_0_ngg_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if (adev->asic_type == CHIP_RAVEN) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v9_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -830,9 +830,9 @@ static int init_over_drive_limits(
|
|||
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock =
|
||||
le16_to_cpu(powerplay_table->ulMaxODEngineClock);
|
||||
le32_to_cpu(powerplay_table->ulMaxODEngineClock);
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
|
||||
le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
|
||||
le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
|
||||
|
||||
hwmgr->platform_descriptor.minOverdriveVDDC = 0;
|
||||
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
|
||||
|
|
|
@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
|
|||
"Trying to Unfreeze MCLK DPM when DPM is disabled",
|
||||
);
|
||||
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
|
||||
PPSMC_MSG_SCLKDPM_UnfreezeLevel),
|
||||
PPSMC_MSG_MCLKDPM_UnfreezeLevel),
|
||||
"Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
|
||||
return -EINVAL);
|
||||
}
|
||||
|
|
|
@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
|
|||
}
|
||||
|
||||
info->par = rfbdev;
|
||||
info->skip_vt_switch = true;
|
||||
|
||||
ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
|
||||
if (ret) {
|
||||
|
|
Loading…
Reference in New Issue