clocksource: Provide timekeeping for efm32 SoCs
An efm32 features 4 16-bit timers with a 10-bit prescaler. This driver provides clocksource and clock event device using one timer instance each. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Uwe Kleine-König
Daniel Lezcano
parent
fdfcab17a2
commit
9c9b781804
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@ -0,0 +1,23 @@
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* EFM32 timer hardware
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The efm32 Giant Gecko SoCs come with four 16 bit timers. Two counters can be
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connected to form a 32 bit counter. Each timer has three Compare/Capture
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channels and can be used as PWM or Quadrature Decoder. Available clock sources
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are the cpu's HFPERCLK (with a 10-bit prescaler) or an external pin.
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Required properties:
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- compatible : Should be efm32,timer
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- reg : Address and length of the register set
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- clocks : Should contain a reference to the HFPERCLK
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Optional properties:
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- interrupts : Reference to the timer interrupt
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Example:
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timer@40010c00 {
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compatible = "efm32,timer";
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reg = <0x40010c00 0x400>;
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interrupts = <14>;
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clocks = <&cmu clk_HFPERCLKTIMER3>;
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};
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@ -71,6 +71,14 @@ config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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help
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Use the always on PRCMU Timer as sched_clock
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config CLKSRC_EFM32
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bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32
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depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
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default ARCH_EFM32
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help
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Support to use the timers of EFM32 SoCs as clock source and clock
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event device.
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config ARM_ARCH_TIMER
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bool
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select CLKSRC_OF if OF
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@ -27,6 +27,7 @@ obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
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obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o
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obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
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obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
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obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
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obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
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obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
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@ -0,0 +1,275 @@
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/*
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* Copyright (C) 2013 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#define TIMERn_CTRL 0x00
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#define TIMERn_CTRL_PRESC(val) (((val) & 0xf) << 24)
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#define TIMERn_CTRL_PRESC_1024 TIMERn_CTRL_PRESC(10)
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#define TIMERn_CTRL_CLKSEL(val) (((val) & 0x3) << 16)
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#define TIMERn_CTRL_CLKSEL_PRESCHFPERCLK TIMERn_CTRL_CLKSEL(0)
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#define TIMERn_CTRL_OSMEN 0x00000010
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#define TIMERn_CTRL_MODE(val) (((val) & 0x3) << 0)
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#define TIMERn_CTRL_MODE_UP TIMERn_CTRL_MODE(0)
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#define TIMERn_CTRL_MODE_DOWN TIMERn_CTRL_MODE(1)
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#define TIMERn_CMD 0x04
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#define TIMERn_CMD_START 0x00000001
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#define TIMERn_CMD_STOP 0x00000002
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#define TIMERn_IEN 0x0c
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#define TIMERn_IF 0x10
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#define TIMERn_IFS 0x14
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#define TIMERn_IFC 0x18
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#define TIMERn_IRQ_UF 0x00000002
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#define TIMERn_TOP 0x1c
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#define TIMERn_CNT 0x24
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struct efm32_clock_event_ddata {
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struct clock_event_device evtdev;
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void __iomem *base;
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unsigned periodic_top;
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};
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static void efm32_clock_event_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evtdev)
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{
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struct efm32_clock_event_ddata *ddata =
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container_of(evtdev, struct efm32_clock_event_ddata, evtdev);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP);
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writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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TIMERn_CTRL_MODE_DOWN,
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ddata->base + TIMERn_CTRL);
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writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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TIMERn_CTRL_OSMEN |
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TIMERn_CTRL_MODE_DOWN,
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ddata->base + TIMERn_CTRL);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static int efm32_clock_event_set_next_event(unsigned long evt,
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struct clock_event_device *evtdev)
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{
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struct efm32_clock_event_ddata *ddata =
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container_of(evtdev, struct efm32_clock_event_ddata, evtdev);
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writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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writel_relaxed(evt, ddata->base + TIMERn_CNT);
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writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD);
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return 0;
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}
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static irqreturn_t efm32_clock_event_handler(int irq, void *dev_id)
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{
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struct efm32_clock_event_ddata *ddata = dev_id;
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writel_relaxed(TIMERn_IRQ_UF, ddata->base + TIMERn_IFC);
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ddata->evtdev.event_handler(&ddata->evtdev);
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return IRQ_HANDLED;
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}
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static struct efm32_clock_event_ddata clock_event_ddata = {
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.evtdev = {
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.name = "efm32 clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_MODE_PERIODIC,
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.set_mode = efm32_clock_event_set_mode,
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.set_next_event = efm32_clock_event_set_next_event,
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.rating = 200,
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},
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};
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static struct irqaction efm32_clock_event_irq = {
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.name = "efm32 clockevent",
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.flags = IRQF_TIMER,
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.handler = efm32_clock_event_handler,
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.dev_id = &clock_event_ddata,
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};
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static int __init efm32_clocksource_init(struct device_node *np)
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{
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struct clk *clk;
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void __iomem *base;
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unsigned long rate;
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int ret;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clocksource (%d)\n", ret);
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goto err_clk_get;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable timer clock for clocksource (%d)\n",
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ret);
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goto err_clk_enable;
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}
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rate = clk_get_rate(clk);
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base = of_iomap(np, 0);
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if (!base) {
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ret = -EADDRNOTAVAIL;
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pr_err("failed to map registers for clocksource\n");
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goto err_iomap;
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}
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writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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TIMERn_CTRL_MODE_UP, base + TIMERn_CTRL);
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writel_relaxed(TIMERn_CMD_START, base + TIMERn_CMD);
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ret = clocksource_mmio_init(base + TIMERn_CNT, "efm32 timer",
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DIV_ROUND_CLOSEST(rate, 1024), 200, 16,
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clocksource_mmio_readl_up);
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if (ret) {
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pr_err("failed to init clocksource (%d)\n", ret);
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goto err_clocksource_init;
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}
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return 0;
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err_clocksource_init:
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iounmap(base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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err_clk_get:
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return ret;
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}
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static int __init efm32_clockevent_init(struct device_node *np)
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{
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struct clk *clk;
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void __iomem *base;
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unsigned long rate;
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int irq;
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int ret;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clockevent (%d)\n", ret);
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goto err_clk_get;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable timer clock for clockevent (%d)\n",
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ret);
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goto err_clk_enable;
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}
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rate = clk_get_rate(clk);
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base = of_iomap(np, 0);
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if (!base) {
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ret = -EADDRNOTAVAIL;
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pr_err("failed to map registers for clockevent\n");
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goto err_iomap;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -ENOENT;
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pr_err("failed to get irq for clockevent\n");
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goto err_get_irq;
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}
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writel_relaxed(TIMERn_IRQ_UF, base + TIMERn_IEN);
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clock_event_ddata.base = base;
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clock_event_ddata.periodic_top = DIV_ROUND_CLOSEST(rate, 1024 * HZ);
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setup_irq(irq, &efm32_clock_event_irq);
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clockevents_config_and_register(&clock_event_ddata.evtdev,
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DIV_ROUND_CLOSEST(rate, 1024),
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0xf, 0xffff);
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return 0;
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err_get_irq:
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iounmap(base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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err_clk_get:
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return ret;
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}
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/*
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* This function asserts that we have exactly one clocksource and one
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* clock_event_device in the end.
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*/
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static void __init efm32_timer_init(struct device_node *np)
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{
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static int has_clocksource, has_clockevent;
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int ret;
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if (!has_clocksource) {
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ret = efm32_clocksource_init(np);
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if (!ret) {
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has_clocksource = 1;
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return;
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}
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}
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if (!has_clockevent) {
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ret = efm32_clockevent_init(np);
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if (!ret) {
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has_clockevent = 1;
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return;
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}
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}
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}
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CLOCKSOURCE_OF_DECLARE(efm32, "efm32,timer", efm32_timer_init);
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