iommu/arm-smmu: prefer stage-1 mappings where we have a choice
For an SMMU that supports both Stage-1 and Stage-2 mappings (but not nested translation), then we should prefer stage-1 mappings as we otherwise rely on the memory attributes of the incoming transactions for IOMMU_CACHE mappings. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -876,12 +876,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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*/
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*/
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cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
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cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
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start = smmu->num_s2_context_banks;
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start = smmu->num_s2_context_banks;
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} else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
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} else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
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cfg->cbar = CBAR_TYPE_S2_TRANS;
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start = 0;
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} else {
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cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
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cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
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start = smmu->num_s2_context_banks;
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start = smmu->num_s2_context_banks;
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} else {
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cfg->cbar = CBAR_TYPE_S2_TRANS;
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start = 0;
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}
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}
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ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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