drivers: PL011: move cts_event workaround into separate function
To avoid lines with more than 80 characters and to make the pl011_int() function more readable, move the workaround out into a separate function. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Naresh Bhat <nbhat@cavium.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1317,6 +1317,25 @@ static void pl011_modem_status(struct uart_amba_port *uap)
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wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
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wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
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}
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}
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static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
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{
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unsigned int dummy_read;
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if (!uap->vendor->cts_event_workaround)
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return;
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/* workaround to make sure that all bits are unlocked.. */
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writew(0x00, uap->port.membase + UART011_ICR);
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/*
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* WA: introduce 26ns(1 uart clk) delay before W1C;
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* single apb access will incur 2 pclk(133.12Mhz) delay,
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* so add 2 dummy reads
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*/
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dummy_read = readw(uap->port.membase + UART011_ICR);
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dummy_read = readw(uap->port.membase + UART011_ICR);
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}
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static irqreturn_t pl011_int(int irq, void *dev_id)
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static irqreturn_t pl011_int(int irq, void *dev_id)
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{
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{
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struct uart_amba_port *uap = dev_id;
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struct uart_amba_port *uap = dev_id;
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@ -1324,25 +1343,13 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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u16 imsc;
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u16 imsc;
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int handled = 0;
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int handled = 0;
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unsigned int dummy_read;
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spin_lock_irqsave(&uap->port.lock, flags);
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spin_lock_irqsave(&uap->port.lock, flags);
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imsc = readw(uap->port.membase + UART011_IMSC);
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imsc = readw(uap->port.membase + UART011_IMSC);
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status = readw(uap->port.membase + UART011_RIS) & imsc;
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status = readw(uap->port.membase + UART011_RIS) & imsc;
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if (status) {
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if (status) {
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do {
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do {
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if (uap->vendor->cts_event_workaround) {
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check_apply_cts_event_workaround(uap);
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/* workaround to make sure that all bits are unlocked.. */
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writew(0x00, uap->port.membase + UART011_ICR);
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/*
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* WA: introduce 26ns(1 uart clk) delay before W1C;
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* single apb access will incur 2 pclk(133.12Mhz) delay,
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* so add 2 dummy reads
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*/
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dummy_read = readw(uap->port.membase + UART011_ICR);
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dummy_read = readw(uap->port.membase + UART011_ICR);
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}
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writew(status & ~(UART011_TXIS|UART011_RTIS|
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writew(status & ~(UART011_TXIS|UART011_RTIS|
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UART011_RXIS),
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UART011_RXIS),
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