ARM: rockchip: add suspend and resume for RK3288
It's a basic version of suspend and resume for rockchip, it only support RK3288 now. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Chris Zhong
Heiko Stuebner
parent
97bf6af1f9
commit
9c1ec8e18c
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@ -1,4 +1,5 @@
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CFLAGS_platsmp.o := -march=armv7-a
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
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obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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@ -0,0 +1,260 @@
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Tony Xie <tony.xie@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/suspend.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regulator/machine.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/suspend.h>
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#include "pm.h"
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/* These enum are option of low power mode */
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enum {
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ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
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ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
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};
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struct rockchip_pm_data {
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const struct platform_suspend_ops *ops;
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int (*init)(struct device_node *np);
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};
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static void __iomem *rk3288_bootram_base;
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static phys_addr_t rk3288_bootram_phy;
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static struct regmap *pmu_regmap;
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static struct regmap *sgrf_regmap;
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static u32 rk3288_pmu_pwr_mode_con;
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static u32 rk3288_sgrf_soc_con0;
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static inline u32 rk3288_l2_config(void)
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{
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u32 l2ctlr;
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asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
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return l2ctlr;
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}
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static void rk3288_config_bootdata(void)
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{
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rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
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rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
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rkpm_bootdata_l2ctlr_f = 1;
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rkpm_bootdata_l2ctlr = rk3288_l2_config();
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}
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static void rk3288_slp_mode_set(int level)
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{
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u32 mode_set, mode_set1;
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regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
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regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
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&rk3288_pmu_pwr_mode_con);
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/* set bit 8 so that system will resume to FAST_BOOT_ADDR */
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regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
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SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE);
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/* booting address of resuming system is from this register value */
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regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
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rk3288_bootram_phy);
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regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
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PMU_ARMINT_WAKEUP_EN);
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mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
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BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
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BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
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BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
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BIT(PMU_SCU_EN);
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mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
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if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
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/* arm off, logic deep sleep */
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mode_set |= BIT(PMU_BUS_PD_EN) |
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BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
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BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
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BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
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mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
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BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
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} else {
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/*
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* arm off, logic normal
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* if pmu_clk_core_src_gate_en is not set,
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* wakeup will be error
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*/
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mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
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}
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regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
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regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
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}
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static void rk3288_slp_mode_set_resume(void)
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{
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regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
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rk3288_pmu_pwr_mode_con);
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regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
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rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE);
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}
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static int rockchip_lpmode_enter(unsigned long arg)
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{
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flush_cache_all();
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cpu_do_idle();
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pr_err("%s: Failed to suspend\n", __func__);
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return 1;
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}
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static int rk3288_suspend_enter(suspend_state_t state)
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{
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local_fiq_disable();
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rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
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cpu_suspend(0, rockchip_lpmode_enter);
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rk3288_slp_mode_set_resume();
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local_fiq_enable();
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return 0;
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}
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static int rk3288_suspend_prepare(void)
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{
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return regulator_suspend_prepare(PM_SUSPEND_MEM);
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}
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static void rk3288_suspend_finish(void)
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{
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if (regulator_suspend_finish())
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pr_err("%s: Suspend finish failed\n", __func__);
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}
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static int rk3288_suspend_init(struct device_node *np)
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{
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struct device_node *sram_np;
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struct resource res;
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int ret;
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pmu_regmap = syscon_node_to_regmap(np);
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if (IS_ERR(pmu_regmap)) {
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pr_err("%s: could not find pmu regmap\n", __func__);
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return PTR_ERR(pmu_regmap);
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}
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sgrf_regmap = syscon_regmap_lookup_by_compatible(
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"rockchip,rk3288-sgrf");
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if (IS_ERR(sgrf_regmap)) {
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pr_err("%s: could not find sgrf regmap\n", __func__);
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return PTR_ERR(pmu_regmap);
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}
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sram_np = of_find_compatible_node(NULL, NULL,
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"rockchip,rk3288-pmu-sram");
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if (!sram_np) {
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pr_err("%s: could not find bootram dt node\n", __func__);
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return -ENODEV;
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}
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rk3288_bootram_base = of_iomap(sram_np, 0);
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if (!rk3288_bootram_base) {
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pr_err("%s: could not map bootram base\n", __func__);
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return -ENOMEM;
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}
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ret = of_address_to_resource(sram_np, 0, &res);
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if (ret) {
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pr_err("%s: could not get bootram phy addr\n", __func__);
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return ret;
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}
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rk3288_bootram_phy = res.start;
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of_node_put(sram_np);
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rk3288_config_bootdata();
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/* copy resume code and data to bootsram */
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memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
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rk3288_bootram_sz);
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return 0;
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}
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static const struct platform_suspend_ops rk3288_suspend_ops = {
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.enter = rk3288_suspend_enter,
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.valid = suspend_valid_only_mem,
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.prepare = rk3288_suspend_prepare,
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.finish = rk3288_suspend_finish,
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};
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static const struct rockchip_pm_data rk3288_pm_data __initconst = {
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.ops = &rk3288_suspend_ops,
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.init = rk3288_suspend_init,
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};
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static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
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{
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.compatible = "rockchip,rk3288-pmu",
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.data = &rk3288_pm_data,
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},
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{ /* sentinel */ },
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};
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void __init rockchip_suspend_init(void)
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{
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const struct rockchip_pm_data *pm_data;
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const struct of_device_id *match;
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struct device_node *np;
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int ret;
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np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
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&match);
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if (!match) {
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pr_err("Failed to find PMU node\n");
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return;
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}
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pm_data = (struct rockchip_pm_data *) match->data;
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if (pm_data->init) {
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ret = pm_data->init(np);
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if (ret) {
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pr_err("%s: matches init error %d\n", __func__, ret);
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return;
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}
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}
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suspend_set_ops(pm_data->ops);
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}
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@ -0,0 +1,99 @@
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Tony Xie <tony.xie@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __MACH_ROCKCHIP_PM_H
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#define __MACH_ROCKCHIP_PM_H
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extern unsigned long rkpm_bootdata_cpusp;
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extern unsigned long rkpm_bootdata_cpu_code;
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extern unsigned long rkpm_bootdata_l2ctlr_f;
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extern unsigned long rkpm_bootdata_l2ctlr;
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extern unsigned long rkpm_bootdata_ddr_code;
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extern unsigned long rkpm_bootdata_ddr_data;
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extern unsigned long rk3288_bootram_sz;
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void rockchip_slp_cpu_resume(void);
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void __init rockchip_suspend_init(void);
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/****** following is rk3288 defined **********/
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#define RK3288_PMU_WAKEUP_CFG0 0x00
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#define RK3288_PMU_WAKEUP_CFG1 0x04
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#define RK3288_PMU_PWRMODE_CON 0x18
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#define RK3288_PMU_OSC_CNT 0x20
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#define RK3288_PMU_PLL_CNT 0x24
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#define RK3288_PMU_STABL_CNT 0x28
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#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
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#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
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#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
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#define RK3288_PMU_CORE_PWRUP_CNT 0x38
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#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
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#define RK3288_PMU_GPU_PWRUP_CNT 0x40
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#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
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#define RK3288_PMU_PWRMODE_CON1 0x90
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#define RK3288_SGRF_SOC_CON0 (0x0000)
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#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
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#define SGRF_FAST_BOOT_EN BIT(8)
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#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
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#define RK3288_CRU_MODE_CON 0x50
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#define RK3288_CRU_SEL0_CON 0x60
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#define RK3288_CRU_SEL1_CON 0x64
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#define RK3288_CRU_SEL10_CON 0x88
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#define RK3288_CRU_SEL33_CON 0xe4
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#define RK3288_CRU_SEL37_CON 0xf4
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/* PMU_WAKEUP_CFG1 bits */
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#define PMU_ARMINT_WAKEUP_EN BIT(0)
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enum rk3288_pwr_mode_con {
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PMU_PWR_MODE_EN = 0,
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PMU_CLK_CORE_SRC_GATE_EN,
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PMU_GLOBAL_INT_DISABLE,
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PMU_L2FLUSH_EN,
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PMU_BUS_PD_EN,
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PMU_A12_0_PD_EN,
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PMU_SCU_EN,
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PMU_PLL_PD_EN,
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PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
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PMU_PWROFF_COMB,
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PMU_ALIVE_USE_LF,
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PMU_PMU_USE_LF,
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PMU_OSC_24M_DIS,
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PMU_INPUT_CLAMP_EN,
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PMU_WAKEUP_RESET_EN,
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PMU_SREF0_ENTER_EN,
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PMU_SREF1_ENTER_EN,
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PMU_DDR0IO_RET_EN,
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PMU_DDR1IO_RET_EN,
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PMU_DDR0_GATING_EN,
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PMU_DDR1_GATING_EN,
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PMU_DDR0IO_RET_DE_REQ,
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PMU_DDR1IO_RET_DE_REQ
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};
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enum rk3288_pwr_mode_con1 {
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PMU_CLR_BUS = 0,
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PMU_CLR_CORE,
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PMU_CLR_CPUP,
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PMU_CLR_ALIVE,
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PMU_CLR_DMA,
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PMU_CLR_PERI,
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PMU_CLR_GPU,
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PMU_CLR_VIDEO,
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PMU_CLR_HEVC,
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PMU_CLR_VIO,
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};
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#endif /* __MACH_ROCKCHIP_PM_H */
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@ -23,9 +23,11 @@
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#include <asm/mach/map.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "core.h"
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#include "pm.h"
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static void __init rockchip_dt_init(void)
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{
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rockchip_suspend_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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platform_device_register_simple("cpufreq-dt", 0, NULL, 0);
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}
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Tony Xie <tony.xie@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
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* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
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*
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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.data
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/*
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* this code will be copied from
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* ddr to sram for system resumeing.
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* so it is ".data section".
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*/
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.align
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ENTRY(rockchip_slp_cpu_resume)
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xf
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cmp r1, #0
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/* olny cpu0 can continue to run, the others is halt here */
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beq cpu0run
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secondary_loop:
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wfe
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b secondary_loop
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cpu0run:
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ldr r3, rkpm_bootdata_l2ctlr_f
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cmp r3, #0
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beq sp_set
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ldr r3, rkpm_bootdata_l2ctlr
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mcr p15, 1, r3, c9, c0, 2
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sp_set:
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ldr sp, rkpm_bootdata_cpusp
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ldr r1, rkpm_bootdata_cpu_code
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bx r1
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ENDPROC(rockchip_slp_cpu_resume)
|
||||
|
||||
/* Parameters filled in by the kernel */
|
||||
|
||||
/* Flag for whether to restore L2CTLR on resume */
|
||||
.global rkpm_bootdata_l2ctlr_f
|
||||
rkpm_bootdata_l2ctlr_f:
|
||||
.long 0
|
||||
|
||||
/* Saved L2CTLR to restore on resume */
|
||||
.global rkpm_bootdata_l2ctlr
|
||||
rkpm_bootdata_l2ctlr:
|
||||
.long 0
|
||||
|
||||
/* CPU resume SP addr */
|
||||
.globl rkpm_bootdata_cpusp
|
||||
rkpm_bootdata_cpusp:
|
||||
.long 0
|
||||
|
||||
/* CPU resume function (physical address) */
|
||||
.globl rkpm_bootdata_cpu_code
|
||||
rkpm_bootdata_cpu_code:
|
||||
.long 0
|
||||
|
||||
ENTRY(rk3288_bootram_sz)
|
||||
.word . - rockchip_slp_cpu_resume
|
||||
Loading…
Reference in New Issue