Blackfin arch: fix bug - build kernel failed at head.S when reprogram clock on all platforms

Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Robin Getz 2008-10-16 23:05:28 +08:00 committed by Bryan Wu
parent ded963a486
commit 9bebeff98e
5 changed files with 5 additions and 5 deletions

View File

@ -88,7 +88,7 @@ ENTRY(_start_dma_code)
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);

View File

@ -79,7 +79,7 @@ ENTRY(_start_dma_code)
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);

View File

@ -88,7 +88,7 @@ ENTRY(_start_dma_code)
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);

View File

@ -95,7 +95,7 @@ ENTRY(_start_dma_code)
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);

View File

@ -78,7 +78,7 @@ ENTRY(_start_dma_code)
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);