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net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES 

The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jisheng Zhang 2016-03-30 19:55:21 +08:00 committed by David S. Miller
parent b7854efce2
commit 9bd9ddb7f8
1 changed files with 1 additions and 9 deletions
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10
drivers/net/ethernet/marvell/mvneta.c
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@ -260,7 +260,6 @@
#define MVNETA_VLAN_TAG_LEN 4 #define MVNETA_VLAN_TAG_LEN 4
#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
#define MVNETA_TX_CSUM_DEF_SIZE 1600 #define MVNETA_TX_CSUM_DEF_SIZE 1600
#define MVNETA_TX_CSUM_MAX_SIZE 9800 #define MVNETA_TX_CSUM_MAX_SIZE 9800
#define MVNETA_ACC_MODE_EXT1 1 #define MVNETA_ACC_MODE_EXT1 1
@ -300,7 +299,7 @@
#define MVNETA_RX_PKT_SIZE(mtu) \ #define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN, \ ETH_HLEN + ETH_FCS_LEN, \
MVNETA_CPU_D_CACHE_LINE_SIZE) L1_CACHE_BYTES)
#define IS_TSO_HEADER(txq, addr) \ #define IS_TSO_HEADER(txq, addr) \
((addr >= txq->tso_hdrs_phys) && \ ((addr >= txq->tso_hdrs_phys) && \
@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
if (rxq->descs == NULL) if (rxq->descs == NULL)
return -ENOMEM; return -ENOMEM;
BUG_ON(rxq->descs !=
PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
rxq->last_desc = rxq->size - 1; rxq->last_desc = rxq->size - 1;
/* Set Rx descriptors queue starting address */ /* Set Rx descriptors queue starting address */
@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp,
if (txq->descs == NULL) if (txq->descs == NULL)
return -ENOMEM; return -ENOMEM;
/* Make sure descriptor address is cache line size aligned */
BUG_ON(txq->descs !=
PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
txq->last_desc = txq->size - 1; txq->last_desc = txq->size - 1;
/* Set maximum bandwidth for enabled TXQs */ /* Set maximum bandwidth for enabled TXQs */