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Merge branches 'upstream/core', 'upstream/xenfs' and 'upstream/evtchn' into upstream/for-linus 

* upstream/core:
  xen/events: Use PIRQ instead of GSI value when unmapping MSI/MSI-X irqs.
  xen: set IO permission early (before early_cpu_init())
  xen: re-enable boot-time ballooning
  xen/balloon: make sure we only include remaining extra ram
  xen/balloon: the balloon_lock is useless
  xen: add extra pages to balloon
  xen/events: use locked set|clear_bit() for cpu_evtchn_mask
  xen/evtchn: clear secondary CPUs' cpu_evtchn_mask[] after restore
  xen: implement XENMEM_machphys_mapping

* upstream/xenfs:
  Revert "xen/privcmd: create address space to allow writable mmaps"
  xen/xenfs: update xenfs_mount for new prototype
  xen: fix header export to userspace
  xen: set vma flag VM_PFNMAP in the privcmd mmap file_op
  xen: xenfs: privcmd: check put_user() return code

* upstream/evtchn:
  xen: make evtchn's name less generic
  xen/evtchn: the evtchn device is non-seekable
  xen/evtchn: add missing static
  xen/evtchn: Fix name of Xen event-channel device
  xen/evtchn: don't do unbind_from_irqhandler under spinlock
  xen/evtchn: remove spurious barrier
  xen/evtchn: ports start enabled
  xen/evtchn: dynamically allocate port_user array
  xen/evtchn: track enabled state for each port
This commit is contained in:
Jeremy Fitzhardinge 2010-11-22 12:22:42 -08:00
parent 1233471572 9045d47ea3 b5d827b641
commit 9b8321531a
1597 changed files with 45039 additions and 58551 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
Documentation/ABI/obsolete/proc-pid-oom_adj Normal file
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@ -0,0 +1,22 @@
What: /proc/<pid>/oom_adj
When: August 2012
Why: /proc/<pid>/oom_adj allows userspace to influence the oom killer's
badness heuristic used to determine which task to kill when the kernel
is out of memory.
The badness heuristic has since been rewritten since the introduction of
this tunable such that its meaning is deprecated. The value was
implemented as a bitshift on a score generated by the badness()
function that did not have any precise units of measure. With the
rewrite, the score is given as a proportion of available memory to the
task allocating pages, so using a bitshift which grows the score
exponentially is, thus, impossible to tune with fine granularity.
A much more powerful interface, /proc/<pid>/oom_score_adj, was
introduced with the oom killer rewrite that allows users to increase or
decrease the badness() score linearly. This interface will replace
/proc/<pid>/oom_adj.
A warning will be emitted to the kernel log if an application uses this
deprecated interface. After it is printed once, future warnings will be
suppressed until the kernel is rebooted.

13
Documentation/DocBook/kgdb.tmpl
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@ -710,7 +710,18 @@ Task Addr Pid Parent [*] cpu State Thread Command
<listitem><para>A simple shell</para></listitem>
<listitem><para>The kdb core command set</para></listitem>
<listitem><para>A registration API to register additional kdb shell commands.</para>
<para>A good example of a self-contained kdb module is the "ftdump" command for dumping the ftrace buffer. See: kernel/trace/trace_kdb.c</para></listitem>
<itemizedlist>
<listitem><para>A good example of a self-contained kdb module
is the "ftdump" command for dumping the ftrace buffer. See:
kernel/trace/trace_kdb.c</para></listitem>
<listitem><para>For an example of how to dynamically register
a new kdb command you can build the kdb_hello.ko kernel module
from samples/kdb/kdb_hello.c. To build this example you can
set CONFIG_SAMPLES=y and CONFIG_SAMPLE_KDB=m in your kernel
config. Later run "modprobe kdb_hello" and the next time you
enter the kdb shell, you can run the "hello"
command.</para></listitem>
</itemizedlist></listitem>
<listitem><para>The implementation for kdb_printf() which
emits messages directly to I/O drivers, bypassing the kernel
log.</para></listitem>

7
Documentation/arm/OMAP/DSS
View File

@ -255,9 +255,10 @@ framebuffer parameters.
Kernel boot arguments
---------------------
vram=<size>
- Amount of total VRAM to preallocate. For example, "10M". omapfb
allocates memory for framebuffers from VRAM.
vram=<size>[,<physaddr>]
- Amount of total VRAM to preallocate and optionally a physical start
memory address. For example, "10M". omapfb allocates memory for
framebuffers from VRAM.
omapfb.mode=<display>:<mode>[,...]
- Default video mode for specified displays. For example,

8
Documentation/block/switching-sched.txt
View File

@ -16,7 +16,7 @@ you can do so by typing:
As of the Linux 2.6.10 kernel, it is now possible to change the
IO scheduler for a given block device on the fly (thus making it possible,
for instance, to set the CFQ scheduler for the system default, but
set a specific device to use the anticipatory or noop schedulers - which
set a specific device to use the deadline or noop schedulers - which
can improve that device's throughput).
To set a specific scheduler, simply do this:
@ -31,7 +31,7 @@ a "cat /sys/block/DEV/queue/scheduler" - the list of valid names
will be displayed, with the currently selected scheduler in brackets:
# cat /sys/block/hda/queue/scheduler
noop anticipatory deadline [cfq]
# echo anticipatory > /sys/block/hda/queue/scheduler
noop deadline [cfq]
# echo deadline > /sys/block/hda/queue/scheduler
# cat /sys/block/hda/queue/scheduler
noop [anticipatory] deadline cfq
noop [deadline] cfq

10
Documentation/feature-removal-schedule.txt
View File

@ -554,3 +554,13 @@ Why: This is a legacy interface which have been replaced by a more
Who: NeilBrown <neilb@suse.de>
----------------------------
What: i2c_adapter.id
When: June 2011
Why: This field is deprecated. I2C device drivers shouldn't change their
behavior based on the underlying I2C adapter. Instead, the I2C
adapter driver should instantiate the I2C devices and provide the
needed platform-specific information.
Who: Jean Delvare <khali@linux-fr.org>
----------------------------

2
Documentation/filesystems/Locking
View File

@ -322,7 +322,6 @@ fl_release_private: yes yes
prototypes:
int (*fl_compare_owner)(struct file_lock *, struct file_lock *);
void (*fl_notify)(struct file_lock *); /* unblock callback */
void (*fl_copy_lock)(struct file_lock *, struct file_lock *);
void (*fl_release_private)(struct file_lock *);
void (*fl_break)(struct file_lock *); /* break_lease callback */
@ -330,7 +329,6 @@ locking rules:
BKL may block
fl_compare_owner: yes no
fl_notify: yes no
fl_copy_lock: yes no
fl_release_private: yes yes
fl_break: yes no

11
Documentation/filesystems/xfs-delayed-logging-design.txt
View File

@ -794,17 +794,6 @@ designed.
Roadmap:
2.6.37 Remove experimental tag from mount option
=> should be roughly 6 months after initial merge
=> enough time to:
=> gain confidence and fix problems reported by early
adopters (a.k.a. guinea pigs)
=> address worst performance regressions and undesired
behaviours
=> start tuning/optimising code for parallelism
=> start tuning/optimising algorithms consuming
excessive CPU time
2.6.39 Switch default mount option to use delayed logging
=> should be roughly 12 months after initial merge
=> enough time to shake out remaining problems before next round of

6
Documentation/i2c/busses/i2c-i801
View File

@ -15,10 +15,14 @@ Supported adapters:
* Intel 82801I (ICH9)
* Intel EP80579 (Tolapai)
* Intel 82801JI (ICH10)
* Intel 3400/5 Series (PCH)
* Intel 5/3400 Series (PCH)
* Intel Cougar Point (PCH)
* Intel Patsburg (PCH)
Datasheets: Publicly available at the Intel website
On Intel Patsburg and later chipsets, both the normal host SMBus controller
and the additional 'Integrated Device Function' controllers are supported.
Authors:
Mark Studebaker <mdsxyz123@yahoo.com>
Jean Delvare <khali@linux-fr.org>

2
Documentation/kernel-parameters.txt
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@ -706,7 +706,7 @@ and is between 256 and 4096 characters. It is defined in the file
arch/x86/kernel/cpu/cpufreq/elanfreq.c.
elevator= [IOSCHED]
Format: {"anticipatory" | "cfq" | "deadline" | "noop"}
Format: {"cfq" | "deadline" | "noop"}
See Documentation/block/as-iosched.txt and
Documentation/block/deadline-iosched.txt for details.

19
Documentation/leds-class.txt
View File

@ -60,15 +60,18 @@ Hardware accelerated blink of LEDs
Some LEDs can be programmed to blink without any CPU interaction. To
support this feature, a LED driver can optionally implement the
blink_set() function (see <linux/leds.h>). If implemented, triggers can
attempt to use it before falling back to software timers. The blink_set()
function should return 0 if the blink setting is supported, or -EINVAL
otherwise, which means that LED blinking will be handled by software.
blink_set() function (see <linux/leds.h>). To set an LED to blinking,
however, it is better to use use the API function led_blink_set(),
as it will check and implement software fallback if necessary.
The blink_set() function should choose a user friendly blinking
value if it is called with *delay_on==0 && *delay_off==0 parameters. In
this case the driver should give back the chosen value through delay_on
and delay_off parameters to the leds subsystem.
To turn off blinking again, use the API function led_brightness_set()
as that will not just set the LED brightness but also stop any software
timers that may have been required for blinking.
The blink_set() function should choose a user friendly blinking value
if it is called with *delay_on==0 && *delay_off==0 parameters. In this
case the driver should give back the chosen value through delay_on and
delay_off parameters to the leds subsystem.
Setting the brightness to zero with brightness_set() callback function
should completely turn off the LED and cancel the previously programmed

88
Documentation/leds/leds-lp5521.txt Normal file
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@ -0,0 +1,88 @@
Kernel driver for lp5521
========================
* National Semiconductor LP5521 led driver chip
* Datasheet: http://www.national.com/pf/LP/LP5521.html
Authors: Mathias Nyman, Yuri Zaporozhets, Samu Onkalo
Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
Description
-----------
LP5521 can drive up to 3 channels. Leds can be controlled directly via
the led class control interface. Channels have generic names:
lp5521:channelx, where x is 0 .. 2
All three channels can be also controlled using the engine micro programs.
More details of the instructions can be found from the public data sheet.
Control interface for the engines:
x is 1 .. 3
enginex_mode : disabled, load, run
enginex_load : store program (visible only in engine load mode)
Example (start to blink the channel 2 led):
cd /sys/class/leds/lp5521:channel2/device
echo "load" > engine3_mode
echo "037f4d0003ff6000" > engine3_load
echo "run" > engine3_mode
stop the engine:
echo "disabled" > engine3_mode
sysfs contains a selftest entry.
The test communicates with the chip and checks that
the clock mode is automatically set to the requested one.
Each channel has its own led current settings.
/sys/class/leds/lp5521:channel0/led_current - RW
/sys/class/leds/lp5521:channel0/max_current - RO
Format: 10x mA i.e 10 means 1.0 mA
example platform data:
Note: chan_nr can have values between 0 and 2.
static struct lp5521_led_config lp5521_led_config[] = {
{
.chan_nr = 0,
.led_current = 50,
.max_current = 130,
}, {
.chan_nr = 1,
.led_current = 0,
.max_current = 130,
}, {
.chan_nr = 2,
.led_current = 0,
.max_current = 130,
}
};
static int lp5521_setup(void)
{
/* setup HW resources */
}
static void lp5521_release(void)
{
/* Release HW resources */
}
static void lp5521_enable(bool state)
{
/* Control of chip enable signal */
}
static struct lp5521_platform_data lp5521_platform_data = {
.led_config = lp5521_led_config,
.num_channels = ARRAY_SIZE(lp5521_led_config),
.clock_mode = LP5521_CLOCK_EXT,
.setup_resources = lp5521_setup,
.release_resources = lp5521_release,
.enable = lp5521_enable,
};
If the current is set to 0 in the platform data, that channel is
disabled and it is not visible in the sysfs.

83
Documentation/leds/leds-lp5523.txt Normal file
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@ -0,0 +1,83 @@
Kernel driver for lp5523
========================
* National Semiconductor LP5523 led driver chip
* Datasheet: http://www.national.com/pf/LP/LP5523.html
Authors: Mathias Nyman, Yuri Zaporozhets, Samu Onkalo
Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
Description
-----------
LP5523 can drive up to 9 channels. Leds can be controlled directly via
the led class control interface. Channels have generic names:
lp5523:channelx where x is 0...8
The chip provides 3 engines. Each engine can control channels without
interaction from the main CPU. Details of the micro engine code can be found
from the public data sheet. Leds can be muxed to different channels.
Control interface for the engines:
x is 1 .. 3
enginex_mode : disabled, load, run
enginex_load : microcode load (visible only in load mode)
enginex_leds : led mux control (visible only in load mode)
cd /sys/class/leds/lp5523:channel2/device
echo "load" > engine3_mode
echo "9d80400004ff05ff437f0000" > engine3_load
echo "111111111" > engine3_leds
echo "run" > engine3_mode
sysfs contains a selftest entry. It measures each channel
voltage level and checks if it looks reasonable. If the level is too high,
the led is missing; if the level is too low, there is a short circuit.
Selftest uses always the current from the platform data.
Each channel contains led current settings.
/sys/class/leds/lp5523:channel2/led_current - RW
/sys/class/leds/lp5523:channel2/max_current - RO
Format: 10x mA i.e 10 means 1.0 mA
Example platform data:
Note - chan_nr can have values between 0 and 8.
static struct lp5523_led_config lp5523_led_config[] = {
{
.chan_nr = 0,
.led_current = 50,
.max_current = 130,
},
...
}, {
.chan_nr = 8,
.led_current = 50,
.max_current = 130,
}
};
static int lp5523_setup(void)
{
/* Setup HW resources */
}
static void lp5523_release(void)
{
/* Release HW resources */
}
static void lp5523_enable(bool state)
{
/* Control chip enable signal */
}
static struct lp5523_platform_data lp5523_platform_data = {
.led_config = lp5523_led_config,
.num_channels = ARRAY_SIZE(lp5523_led_config),
.clock_mode = LP5523_CLOCK_EXT,
.setup_resources = lp5523_setup,
.release_resources = lp5523_release,
.enable = lp5523_enable,
};

9
Documentation/networking/ip-sysctl.txt
View File

@ -20,6 +20,15 @@ ip_no_pmtu_disc - BOOLEAN
min_pmtu - INTEGER
default 562 - minimum discovered Path MTU
route/max_size - INTEGER
Maximum number of routes allowed in the kernel. Increase
this when using large numbers of interfaces and/or routes.
neigh/default/gc_thresh3 - INTEGER
Maximum number of neighbor entries allowed. Increase this
when using large numbers of interfaces and when communicating
with large numbers of directly-connected peers.
mtu_expires - INTEGER
Time, in seconds, that cached PMTU information is kept.

4
Documentation/rbtree.txt
View File

@ -21,8 +21,8 @@ three rotations, respectively, to balance the tree), with slightly slower
To quote Linux Weekly News:
There are a number of red-black trees in use in the kernel.
The anticipatory, deadline, and CFQ I/O schedulers all employ
rbtrees to track requests; the packet CD/DVD driver does the same.
The deadline and CFQ I/O schedulers employ rbtrees to
track requests; the packet CD/DVD driver does the same.
The high-resolution timer code uses an rbtree to organize outstanding
timer requests. The ext3 filesystem tracks directory entries in a
red-black tree. Virtual memory areas (VMAs) are tracked with red-black

47
Documentation/scsi/ChangeLog.megaraid_sas
View File

@ -1,3 +1,50 @@
1 Release Date : Thur. May 03, 2010 09:12:45 PST 2009 -
(emaild-id:megaraidlinux@lsi.com)
Bo Yang
2 Current Version : 00.00.04.31-rc1
3 Older Version : 00.00.04.17.1-rc1
1. Add the Online Controller Reset (OCR) to the Driver.
OCR is the new feature for megaraid_sas driver which
will allow the fw to do the chip reset which will not
affact the OS behavious.
To add the OCR support, driver need to do:
a). reset the controller chips -- Xscale and Gen2 which
will change the function calls and add the reset function
related to this two chips.
b). during the reset, driver will store the pending cmds
which not returned by FW to driver's pending queue. Driver
will re-issue those pending cmds again to FW after the OCR
finished.
c). In driver's timeout routine, driver will report to
OS as reset. Also driver's queue routine will block the
cmds until the OCR finished.
d). in Driver's ISR routine, if driver get the FW state as
state change, FW in Failure status and FW support online controller
reset (OCR), driver will start to do the controller reset.
e). In driver's IOCTL routine, the application cmds will wait for the
OCR to finish, then issue the cmds to FW.
f). Before driver kill adapter, driver will do last chance of
OCR to see if driver can bring back the FW.
2. Add the support update flag to the driver to tell LSI megaraid_sas
application which driver will support the device update. So application
will not need to do the device update after application add/del the device
from the system.
3. In driver's timeout routine, driver will do three time reset if fw is in
failed state. Driver will kill adapter if can't bring back FW after the
this three times reset.
4. Add the input parameter max_sectors to 1MB support to our GEN2 controller.
customer can use the input paramenter max_sectors to add 1MB support to GEN2
controller.
1 Release Date : Thur. Oct 29, 2009 09:12:45 PST 2009 -
(emaild-id:megaraidlinux@lsi.com)
Bo Yang

14
Documentation/sysctl/kernel.txt
View File

@ -28,6 +28,7 @@ show up in /proc/sys/kernel:
- core_uses_pid
- ctrl-alt-del
- dentry-state
- dmesg_restrict
- domainname
- hostname
- hotplug
@ -213,6 +214,19 @@ to decide what to do with it.
==============================================================
dmesg_restrict:
This toggle indicates whether unprivileged users are prevented from using
dmesg(8) to view messages from the kernel's log buffer. When
dmesg_restrict is set to (0) there are no restrictions. When
dmesg_restrict is set set to (1), users must have CAP_SYS_ADMIN to use
dmesg(8).
The kernel config option CONFIG_SECURITY_DMESG_RESTRICT sets the default
value of dmesg_restrict.
==============================================================
domainname & hostname:
These files can be used to set the NIS/YP domainname and the

20
MAINTAINERS
View File

@ -161,7 +161,7 @@ M: Greg Kroah-Hartman <gregkh@suse.de>
L: linux-serial@vger.kernel.org
W: http://serial.sourceforge.net
S: Maintained
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
F: drivers/serial/8250*
F: include/linux/serial_8250.h
@ -945,7 +945,7 @@ M: Magnus Damm <magnus.damm@gmail.com>
L: linux-sh@vger.kernel.org
W: http://oss.renesas.com
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git rmobile-latest
S: Supported
F: arch/arm/mach-shmobile/
F: drivers/sh/
@ -1757,6 +1757,7 @@ L: linux-cris-kernel@axis.com
W: http://developer.axis.com
S: Maintained
F: arch/cris/
F: drivers/serial/crisv10.*
CRYPTO API
M: Herbert Xu <herbert@gondor.apana.org.au>
@ -2434,6 +2435,7 @@ F: drivers/net/wan/sdla.c
FRAMEBUFFER LAYER
L: linux-fbdev@vger.kernel.org
W: http://linux-fbdev.sourceforge.net/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6.git
S: Orphan
F: Documentation/fb/
F: drivers/video/fb*
@ -5675,7 +5677,7 @@ S: Maintained
STAGING SUBSYSTEM
M: Greg Kroah-Hartman <gregkh@suse.de>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-next-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6.git
L: devel@driverdev.osuosl.org
S: Maintained
F: drivers/staging/
@ -5704,7 +5706,7 @@ M: Paul Mundt <lethal@linux-sh.org>
L: linux-sh@vger.kernel.org
W: http://www.linux-sh.org
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git sh-latest
S: Supported
F: Documentation/sh/
F: arch/sh/
@ -5909,7 +5911,7 @@ S: Maintained
TTY LAYER
M: Greg Kroah-Hartman <gregkh@suse.de>
S: Maintained
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
F: drivers/char/tty_*
F: drivers/serial/serial_core.c
F: include/linux/serial_core.h
@ -6232,7 +6234,7 @@ USB SUBSYSTEM
M: Greg Kroah-Hartman <gregkh@suse.de>
L: linux-usb@vger.kernel.org
W: http://www.linux-usb.org
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6.git
S: Supported
F: Documentation/usb/
F: drivers/net/usb/
@ -6597,14 +6599,14 @@ F: drivers/platform/x86
XEN PCI SUBSYSTEM
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xensource.com
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
S: Supported
F: arch/x86/pci/*xen*
F: drivers/pci/*xen*
XEN SWIOTLB SUBSYSTEM
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xensource.com
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
S: Supported
F: arch/x86/xen/*swiotlb*
F: drivers/xen/*swiotlb*
@ -6612,7 +6614,7 @@ F: drivers/xen/*swiotlb*
XEN HYPERVISOR INTERFACE
M: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xen.org
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
L: virtualization@lists.osdl.org
S: Supported
F: arch/x86/xen/

7
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 36
EXTRAVERSION =
SUBLEVEL = 37
EXTRAVERSION = -rc2
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*
@ -204,6 +204,9 @@ ifeq ($(ARCH),x86_64)
endif
# Additional ARCH settings for sparc
ifeq ($(ARCH),sparc32)
SRCARCH := sparc
endif
ifeq ($(ARCH),sparc64)
SRCARCH := sparc
endif

14
arch/Kconfig
View File

@ -42,6 +42,20 @@ config KPROBES
for kernel debugging, non-intrusive instrumentation and testing.
If in doubt, say "N".
config JUMP_LABEL
bool "Optimize trace point call sites"
depends on HAVE_ARCH_JUMP_LABEL
help
If it is detected that the compiler has support for "asm goto",
the kernel will compile trace point locations with just a
nop instruction. When trace points are enabled, the nop will
be converted to a jump to the trace function. This technique
lowers overhead and stress on the branch prediction of the
processor.
On i386, options added to the compiler flags may increase
the size of the kernel slightly.
config OPTPROBES
def_bool y
depends on KPROBES && HAVE_OPTPROBES

40
arch/arm/Kconfig
View File

@ -6,7 +6,7 @@ config ARM
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_ATOMIC64 if (!CPU_32v6K)
select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
@ -646,7 +646,7 @@ config ARCH_S3C2410
select ARCH_HAS_CPUFREQ
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C2410_I2C if I2C
help
Samsung S3C2410X CPU based systems, such as the Simtec Electronics
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
@ -676,8 +676,8 @@ config ARCH_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select SAMSUNG_GPIOLIB_4BIT
select HAVE_S3C2410_I2C
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S3C64XX series based systems
@ -686,10 +686,10 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
help
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
@ -700,7 +700,7 @@ config ARCH_S5P6442
select GENERIC_GPIO
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5P6442 CPU based systems
@ -711,31 +711,37 @@ config ARCH_S5PC100
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PC100 series based systems
config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_S5PV310
bool "Samsung S5PV310/S5PC210"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV310 series based systems
@ -1662,6 +1668,12 @@ if ARCH_HAS_CPUFREQ
source "drivers/cpufreq/Kconfig"
config CPU_FREQ_IMX
tristate "CPUfreq driver for i.MX CPUs"
depends on ARCH_MXC && CPU_FREQ
help
This enables the CPUfreq driver for i.MX CPUs.
config CPU_FREQ_SA1100
bool

28
arch/arm/common/gic.c
View File

@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all interrupts.
* Set priority on all global interrupts.
*/
for (i = 0; i < max_irq; i += 4)
for (i = 32; i < max_irq; i += 4)
writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts.
* Disable all interrupts. Leave the PPI and SGIs alone
* as these enables are banked registers.
*/
for (i = 0; i < max_irq; i += 32)
for (i = 32; i < max_irq; i += 32)
writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
{
void __iomem *dist_base;
int i;
if (gic_nr >= MAX_GIC_NR)
BUG();
dist_base = gic_data[gic_nr].dist_base;
BUG_ON(!dist_base);
gic_data[gic_nr].cpu_base = base;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
writel(0xf0, base + GIC_CPU_PRIMASK);
writel(1, base + GIC_CPU_CTRL);
}

1
arch/arm/configs/mx51_defconfig
View File

@ -82,6 +82,7 @@ CONFIG_FEC=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_EVBUG=m
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ELANTECH=y

13
arch/arm/include/asm/hardware/cache-l2x0.h
View File

@ -21,9 +21,6 @@
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
@ -53,6 +50,16 @@
#define L2X0_LINE_DATA 0xF10
#define L2X0_LINE_TAG 0xF30
#define L2X0_DEBUG_CTRL 0xF40
#define L2X0_PREFETCH_CTRL 0xF60
#define L2X0_POWER_CTRL 0xF80
#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
#define L2X0_STNDBY_MODE_EN (1 << 0)
/* Registers shifts and masks */
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);

2
arch/arm/include/asm/hardware/it8152.h
View File

@ -75,7 +75,7 @@ extern unsigned long it8152_base_address;
IT8152_PD_IRQ(1) USB (USBR)
IT8152_PD_IRQ(0) Audio controller (ACR)
*/
#define IT8152_IRQ(x) (IRQ_BOARD_END + (x))
#define IT8152_IRQ(x) (IRQ_BOARD_START + (x))
/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
#define IT8152_LD_IRQ_COUNT 9

5
arch/arm/include/asm/kgdb.h
View File

@ -70,7 +70,8 @@ extern int kgdb_fault_expected;
#define _GP_REGS 16
#define _FP_REGS 8
#define _EXTRA_REGS 2
#define DBG_MAX_REG_NUM (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
#define DBG_MAX_REG_NUM (_GP_REGS + _FP_REGS + _EXTRA_REGS)
#define KGDB_MAX_NO_CPUS 1
#define BUFMAX 400
@ -93,7 +94,7 @@ extern int kgdb_fault_expected;
#define _SPT 13
#define _LR 14
#define _PC 15
#define _CPSR (DBG_MAX_REG_NUM - 1)
#define _CPSR (GDB_MAX_REGS - 1)
/*
* So that we can denote the end of a frame for tracing,

7
arch/arm/include/asm/memblock.h
View File

@ -1,13 +1,6 @@
#ifndef _ASM_ARM_MEMBLOCK_H
#define _ASM_ARM_MEMBLOCK_H
#ifdef CONFIG_MMU
extern phys_addr_t lowmem_end_addr;
#define MEMBLOCK_REAL_LIMIT lowmem_end_addr
#else
#define MEMBLOCK_REAL_LIMIT 0
#endif
struct meminfo;
struct machine_desc;

24
arch/arm/include/asm/outercache.h
View File

@ -25,6 +25,9 @@ struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
void (*flush_range)(unsigned long, unsigned long);
void (*flush_all)(void);
void (*inv_all)(void);
void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
void (*sync)(void);
#endif
@ -50,6 +53,24 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
outer_cache.flush_range(start, end);
}
static inline void outer_flush_all(void)
{
if (outer_cache.flush_all)
outer_cache.flush_all();
}
static inline void outer_inv_all(void)
{
if (outer_cache.inv_all)
outer_cache.inv_all();
}
static inline void outer_disable(void)
{
if (outer_cache.disable)
outer_cache.disable();
}
#else
static inline void outer_inv_range(unsigned long start, unsigned long end)
@ -58,6 +79,9 @@ static inline void outer_clean_range(unsigned long start, unsigned long end)
{ }
static inline void outer_flush_range(unsigned long start, unsigned long end)
{ }
static inline void outer_flush_all(void) { }
static inline void outer_inv_all(void) { }
static inline void outer_disable(void) { }
#endif

3
arch/arm/kernel/hw_breakpoint.c
View File

@ -748,8 +748,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
breakpoint_handler(addr, regs);
break;
case ARM_ENTRY_ASYNC_WATCHPOINT:
WARN_ON("Asynchronous watchpoint exception taken. "
"Debugging results may be unreliable");
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
case ARM_ENTRY_SYNC_WATCHPOINT:
watchpoint_handler(addr, regs);
break;

2
arch/arm/kernel/kgdb.c
View File

@ -79,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
return;
/* Initialize to zero */
for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
for (regno = 0; regno < GDB_MAX_REGS; regno++)
gdb_regs[regno] = 0;
/* Otherwise, we have only some registers from switch_to() */

3
arch/arm/kernel/machine_kexec.c
View File

@ -78,7 +78,10 @@ void machine_kexec(struct kimage *image)
local_fiq_disable();
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
flush_cache_all();
outer_flush_all();
outer_disable();
cpu_proc_fin();
outer_inv_all();
flush_cache_all();
cpu_reset(reboot_code_buffer_phys);
}

2
arch/arm/kernel/perf_event.c
View File

@ -1749,7 +1749,7 @@ static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
enum armv7_counters counter)
{
int ret;
int ret = 0;
if (counter == ARMV7_CYCLE_COUNTER)
ret = pmnc & ARMV7_FLAG_C;

2
arch/arm/kernel/stacktrace.c
View File

@ -28,7 +28,7 @@ int notrace unwind_frame(struct stackframe *frame)
/* only go to a higher address on the stack */
low = frame->sp;
high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
high = ALIGN(low, THREAD_SIZE);
/* check current frame pointer is within bounds */
if (fp < (low + 12) || fp + 4 >= high)

5
arch/arm/kernel/traps.c
View File

@ -53,10 +53,7 @@ static void dump_mem(const char *, const char *, unsigned long, unsigned long);
void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
{
#ifdef CONFIG_KALLSYMS
char sym1[KSYM_SYMBOL_LEN], sym2[KSYM_SYMBOL_LEN];
sprint_symbol(sym1, where);
sprint_symbol(sym2, from);
printk("[<%08lx>] (%s) from [<%08lx>] (%s)\n", where, sym1, from, sym2);
printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
#else
printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
#endif

2
arch/arm/kernel/unwind.c
View File

@ -279,7 +279,7 @@ int unwind_frame(struct stackframe *frame)
/* only go to a higher address on the stack */
low = frame->sp;
high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
high = ALIGN(low, THREAD_SIZE);
pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
frame->pc, frame->lr, frame->sp);

1
arch/arm/kernel/vmlinux.lds.S
View File

@ -113,6 +113,7 @@ SECTIONS
*(.rodata.*)
*(.glue_7)
*(.glue_7t)
. = ALIGN(4);
*(.got) /* Global offset table */
ARM_CPU_KEEP(PROC_INFO)
}

111
arch/arm/mach-ep93xx/include/mach/dma.h
View File

@ -1,5 +1,13 @@
/*
* arch/arm/mach-ep93xx/include/mach/dma.h
/**
* DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
*
* The EP93xx DMA M2P subsystem handles DMA transfers between memory and
* peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
* See chapter 10 of the EP93xx users guide for full details on the DMA M2P
* engine.
*
* See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
*
*/
#ifndef __ASM_ARCH_DMA_H
@ -8,12 +16,34 @@
#include <linux/list.h>
#include <linux/types.h>
/**
* struct ep93xx_dma_buffer - Information about a buffer to be transferred
* using the DMA M2P engine
*
* @list: Entry in DMA buffer list
* @bus_addr: Physical address of the buffer
* @size: Size of the buffer in bytes
*/
struct ep93xx_dma_buffer {
struct list_head list;
u32 bus_addr;
u16 size;
};
/**
* struct ep93xx_dma_m2p_client - Information about a DMA M2P client
*
* @name: Unique name for this client
* @flags: Client flags
* @cookie: User data to pass to callback functions
* @buffer_started: Non NULL function to call when a transfer is started.
* The arguments are the user data cookie and the DMA
* buffer which is starting.
* @buffer_finished: Non NULL function to call when a transfer is completed.
* The arguments are the user data cookie, the DMA buffer
* which has completed, and a boolean flag indicating if
* the transfer had an error.
*/
struct ep93xx_dma_m2p_client {
char *name;
u8 flags;
@ -24,10 +54,11 @@ struct ep93xx_dma_m2p_client {
struct ep93xx_dma_buffer *buf,
int bytes, int error);
/* Internal to the DMA code. */
/* private: Internal use only */
void *channel;
};
/* DMA M2P ports */
#define EP93XX_DMA_M2P_PORT_I2S1 0x00
#define EP93XX_DMA_M2P_PORT_I2S2 0x01
#define EP93XX_DMA_M2P_PORT_AAC1 0x02
@ -39,18 +70,80 @@ struct ep93xx_dma_m2p_client {
#define EP93XX_DMA_M2P_PORT_UART3 0x08
#define EP93XX_DMA_M2P_PORT_IRDA 0x09
#define EP93XX_DMA_M2P_PORT_MASK 0x0f
#define EP93XX_DMA_M2P_TX 0x00
#define EP93XX_DMA_M2P_RX 0x10
#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20
#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40
#define EP93XX_DMA_M2P_ERROR_MASK 0x60
int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
/* DMA M2P client flags */
#define EP93XX_DMA_M2P_TX 0x00 /* Memory to peripheral */
#define EP93XX_DMA_M2P_RX 0x10 /* Peripheral to memory */
/*
* DMA M2P client error handling flags. See the EP93xx users guide
* documentation on the DMA M2P CONTROL register for more details
*/
#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 /* Abort on peripheral error */
#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 /* Ignore peripheral errors */
#define EP93XX_DMA_M2P_ERROR_MASK 0x60 /* Mask of error bits */
/**
* ep93xx_dma_m2p_client_register - Register a client with the DMA M2P
* subsystem
*
* @m2p: Client information to register
* returns 0 on success
*
* The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
* client
*/
int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
/**
* ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P
* subsystem
*
* @m2p: Client to unregister
*
* Any transfers currently in progress will be completed in hardware, but
* ignored in software.
*/
void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
/**
* ep93xx_dma_m2p_submit - Submit a DMA M2P transfer
*
* @m2p: DMA Client to submit the transfer on
* @buf: DMA Buffer to submit
*
* If the current or next transfer positions are free on the M2P client then
* the transfer is started immediately. If not, the transfer is added to the
* list of pending transfers. This function must not be called from the
* buffer_finished callback for an M2P channel.
*
*/
void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
/**
* ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list
* for an M2P channel
*
* @m2p: DMA Client to submit the transfer on
* @buf: DMA Buffer to submit
*
* This function must only be called from the buffer_finished callback for an
* M2P channel. It is commonly used to add the next transfer in a chained list
* of DMA transfers.
*/
void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
/**
* ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client
*
* @m2p: DMA client to flush transfers on
*
* Any transfers currently in progress will be completed in hardware, but
* ignored in software.
*
*/
void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
#endif /* __ASM_ARCH_DMA_H */

38
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -23,16 +23,20 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
#define SD1_EN_GPIO (GPIO_PORTB + 25)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
@ -58,6 +62,14 @@ static const int mx27pdk_pins[] __initconst = {
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* SDHC1 */
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -85,13 +97,39 @@ static struct matrix_keymap_data mx27_3ds_keymap_data = {
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}
static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOB(26), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
.init = mx27_3ds_sdhc1_init,
.exit = mx27_3ds_sdhc1_exit,
};
static void mx27_3ds_sdhc1_enable_level_translator(void)
{
/* Turn on TXB0108 OE pin */
gpio_request(SD1_EN_GPIO, "sd1_enable");
gpio_direction_output(SD1_EN_GPIO, 1);
}
static void __init mx27pdk_init(void)
{
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
}
static void __init mx27pdk_timer_init(void)

2
arch/arm/mach-ixp2000/core.c
View File

@ -197,7 +197,7 @@ unsigned long ixp2000_gettimeoffset (void)
return offset / ticks_per_usec;
}
static int ixp2000_timer_interrupt(int irq, void *dev_id)
static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
{
/* clear timer 1 */
ixp2000_reg_wrb(IXP2000_T1_CLR, 1);

7
arch/arm/mach-kirkwood/common.c
View File

@ -854,10 +854,9 @@ int __init kirkwood_find_tclk(void)
kirkwood_pcie_id(&dev, &rev);
if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
rev == MV88F6281_REV_A1)) ||
(dev == MV88F6282_DEV_ID))
return 200000000;
if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
return 200000000;
return 166666667;
}

2
arch/arm/mach-kirkwood/d2net_v2-setup.c
View File

@ -225,5 +225,5 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
.init_machine = d2net_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END

14
arch/arm/mach-kirkwood/lacie_v2-common.c
View File

@ -111,17 +111,3 @@ void __init lacie_v2_hdd_power_init(int hdd_num)
pr_err("Failed to power up HDD%d\n", i + 1);
}
}
/*****************************************************************************
* Timer
****************************************************************************/
static void lacie_v2_timer_init(void)
{
kirkwood_tclk = 166666667;
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer lacie_v2_timer = {
.init = lacie_v2_timer_init,
};

2
arch/arm/mach-kirkwood/lacie_v2-common.h
View File

@ -13,6 +13,4 @@ void lacie_v2_register_flash(void);
void lacie_v2_register_i2c_devices(void);
void lacie_v2_hdd_power_init(int hdd_num);
extern struct sys_timer lacie_v2_timer;
#endif

4
arch/arm/mach-kirkwood/mpp.c
View File

@ -59,7 +59,7 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
}
printk("\n");
while (*mpp_list) {
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
@ -88,8 +88,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
mpp_list++;
}
printk(KERN_DEBUG " final MPP regs:");

6
arch/arm/mach-kirkwood/netspace_v2-setup.c
View File

@ -262,7 +262,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -272,7 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -282,6 +282,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif

4
arch/arm/mach-kirkwood/netxbig_v2-setup.c
View File

@ -403,7 +403,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -413,6 +413,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif

14
arch/arm/mach-kirkwood/ts41x-setup.c
View File

@ -27,6 +27,10 @@
#include "mpp.h"
#include "tsx1x-common.h"
/* for the PCIe reset workaround */
#include <plat/pcie.h>
#define QNAP_TS41X_JUMPER_JP1 45
static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
static int __init ts41x_pci_init(void)
{
if (machine_is_ts41x())
if (machine_is_ts41x()) {
/*
* Without this explicit reset, the PCIe SATA controller
* (Marvell 88sx7042/sata_mv) is known to stop working
* after a few minutes.
*/
orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
kirkwood_pcie_init(KW_PCIE0);
}
return 0;
}

3
arch/arm/mach-mmp/include/mach/cputype.h
View File

@ -46,7 +46,8 @@ static inline int cpu_is_pxa910(void)
#ifdef CONFIG_CPU_MMP2
static inline int cpu_is_mmp2(void)
{
return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
return (((read_cpuid_id() >> 8) & 0xff) == 0x58);
}
#else
#define cpu_is_mmp2() (0)
#endif

9
arch/arm/mach-msm/Kconfig
View File

@ -6,6 +6,7 @@ choice
config ARCH_MSM7X00A
bool "MSM7x00A / MSM7x01A"
select MACH_TROUT if !MACH_HALIBUT
select ARCH_MSM_ARM11
select MSM_SMD
select MSM_SMD_PKG3
@ -15,34 +16,34 @@ config ARCH_MSM7X00A
config ARCH_MSM7X30
bool "MSM7x30"
select MACH_MSM7X30_SURF # if !
select ARCH_MSM_SCORPION
select MSM_SMD
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_DEKKERS
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_QSD8X50
bool "QSD8X50"
select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
select ARCH_MSM_SCORPION
select MSM_SMD
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_LDREX
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM8X60
bool "MSM8X60"
select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
&& !MACH_MSM8X60_FFA)
select ARM_GIC
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
&& !MACH_MSM8X60_FFA)
endchoice

1
arch/arm/mach-msm/board-halibut.c
View File

@ -83,7 +83,6 @@ static void __init halibut_fixup(struct machine_desc *desc, struct tag *tags,
{
mi->nr_banks=1;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = (101*1024*1024);
}

15
arch/arm/mach-msm/include/mach/debug-macro.S
View File

@ -19,7 +19,7 @@
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
.macro addruart, rp, rv
ldr \rp, =MSM_DEBUG_UART_PHYS
ldr \rv, =MSM_DEBUG_UART_BASE
@ -36,7 +36,18 @@
tst \rd, #0x04
beq 1001b
.endm
#else
.macro addruart, rp, rv
mov \rv, #0xff000000
orr \rv, \rv, #0x00f00000
.endm
.macro senduart,rd,rx
.endm
.macro waituart,rd,rx
.endm
#endif
.macro busyuart,rd,rx
.endm
#endif

22
arch/arm/mach-msm/iommu_dev.c
View File

@ -128,7 +128,7 @@ static void msm_iommu_reset(void __iomem *base)
static int msm_iommu_probe(struct platform_device *pdev)
{
struct resource *r;
struct resource *r, *r2;
struct clk *iommu_clk;
struct msm_iommu_drvdata *drvdata;
struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
@ -183,27 +183,27 @@ static int msm_iommu_probe(struct platform_device *pdev)
len = r->end - r->start + 1;
r = request_mem_region(r->start, len, r->name);
if (!r) {
r2 = request_mem_region(r->start, len, r->name);
if (!r2) {
pr_err("Could not request memory region: "
"start=%p, len=%d\n", (void *) r->start, len);
ret = -EBUSY;
goto fail;
}
regs_base = ioremap(r->start, len);
regs_base = ioremap(r2->start, len);
if (!regs_base) {
pr_err("Could not ioremap: start=%p, len=%d\n",
(void *) r->start, len);
(void *) r2->start, len);
ret = -EBUSY;
goto fail;
goto fail_mem;
}
irq = platform_get_irq_byname(pdev, "secure_irq");
if (irq < 0) {
ret = -ENODEV;
goto fail;
goto fail_io;
}
mb();
@ -211,14 +211,14 @@ static int msm_iommu_probe(struct platform_device *pdev)
if (GET_IDR(regs_base) == 0) {
pr_err("Invalid IDR value detected\n");
ret = -ENODEV;
goto fail;
goto fail_io;
}
ret = request_irq(irq, msm_iommu_fault_handler, 0,
"msm_iommu_secure_irpt_handler", drvdata);
if (ret) {
pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
goto fail;
goto fail_io;
}
msm_iommu_reset(regs_base);
@ -237,6 +237,10 @@ static int msm_iommu_probe(struct platform_device *pdev)
return 0;
fail_io:
iounmap(regs_base);
fail_mem:
release_mem_region(r->start, len);
fail:
kfree(drvdata);
return ret;

2
arch/arm/mach-msm/timer.c
View File

@ -137,7 +137,7 @@ static struct msm_clock msm_clocks[] = {
.rating = 200,
.read = msm_gpt_read,
.mask = CLOCKSOURCE_MASK(32),
.shift = 24,
.shift = 17,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
},
.irq = {

4
arch/arm/mach-mv78xx0/mpp.c
View File

@ -54,7 +54,7 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
}
printk("\n");
while (*mpp_list) {
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
@ -83,8 +83,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
mpp_list++;
}
printk(KERN_DEBUG " final MPP regs:");

1
arch/arm/mach-mx25/Kconfig
View File

@ -6,6 +6,7 @@ config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"

10
arch/arm/mach-mx25/mach-mx25_3ds.c
View File

@ -96,6 +96,14 @@ static struct pad_desc mx25pdk_pads[] = {
MX25_PAD_KPP_COL1__KPP_COL1,
MX25_PAD_KPP_COL2__KPP_COL2,
MX25_PAD_KPP_COL3__KPP_COL3,
/* SD1 */
MX25_PAD_SD1_CMD__SD1_CMD,
MX25_PAD_SD1_CLK__SD1_CLK,
MX25_PAD_SD1_DATA0__SD1_DATA0,
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
@ -193,6 +201,8 @@ static void __init mx25pdk_init(void)
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
imx25_add_esdhc(0, NULL);
}
static void __init mx25pdk_timer_init(void)

2
arch/arm/mach-mx3/Kconfig
View File

@ -143,8 +143,10 @@ config MACH_ARMADILLO5X0
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
default n
help
Include support for MX35PDK platform. This includes specific

16
arch/arm/mach-mx3/devices.c
View File

@ -72,24 +72,24 @@ struct platform_device mxc_w1_master_device = {
#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
{
.start = MMC_SDHC1_BASE_ADDR,
.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.start = MX31_MMC_SDHC1_BASE_ADDR,
.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_MMC_SDHC1,
.end = MXC_INT_MMC_SDHC1,
.start = MX31_INT_MMC_SDHC1,
.end = MX31_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxcsdhc1_resources[] = {
{
.start = MMC_SDHC2_BASE_ADDR,
.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.start = MX31_MMC_SDHC2_BASE_ADDR,
.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_MMC_SDHC2,
.end = MXC_INT_MMC_SDHC2,
.start = MX31_INT_MMC_SDHC2,
.end = MX31_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};

38
arch/arm/mach-mx3/mach-mx31_3ds.c
View File

@ -38,39 +38,9 @@
#include "devices-imx31.h"
#include "devices.h"
/* Definitions for components on the Debug board */
/* Base address of CPLD controller on the Debug board */
#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
/* LAN9217 ethernet base address */
#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
/* CPLD config and interrupt base address */
#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
/* status, interrupt */
#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
/* CPLD code version */
#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
#define MXC_MAX_EXP_IO_LINES 16
/*
* This file contains the board-specific initialization routines.
*/
@ -272,7 +242,7 @@ static void __init mxc_board_init(void)
imx31_add_imx_uart0(&uart_pdata);
imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
imx31_add_spi_imx0(&spi1_pdata);
imx31_add_spi_imx1(&spi1_pdata);
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
@ -281,9 +251,9 @@ static void __init mxc_board_init(void)
mx31_3ds_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
printk(KERN_WARNING "Init of the debugboard failed, all "
"devices on the board are unusable.\n");
if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
printk(KERN_WARNING "Init of the debug board failed, all "
"devices on the debug board are unusable.\n");
}
static void __init mx31_3ds_timer_init(void)

16
arch/arm/mach-mx3/mach-mx35_3ds.c
View File

@ -38,11 +38,15 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -108,6 +112,13 @@ static struct pad_desc mx35pdk_pads[] = {
/* USBH1 */
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
/* SDCARD */
MX35_PAD_SD1_CMD__ESDHC1_CMD,
MX35_PAD_SD1_CLK__ESDHC1_CLK,
MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
};
/* OTG config */
@ -140,6 +151,11 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_esdhc(0, NULL);
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all "
"devices on the debugboard are unusable.\n");
}
static void __init mx35pdk_timer_init(void)

2
arch/arm/mach-mx5/Kconfig
View File

@ -6,6 +6,7 @@ config ARCH_MX51
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
comment "MX5 platforms:"
@ -13,6 +14,7 @@ config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_ESDHC
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its

1
arch/arm/mach-mx5/Makefile
View File

@ -5,6 +5,7 @@
# Object file lists.
obj-y := cpu.o mm.o clock-mx51.o devices.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o

49
arch/arm/mach-mx5/board-mx51_babbage.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
@ -18,6 +18,8 @@
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/fec.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <mach/common.h>
#include <mach/hardware.h>
@ -32,11 +34,13 @@
#include "devices-imx51.h"
#include "devices.h"
#include "cpu_op-mx51.h"
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
@ -46,6 +50,21 @@
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
static struct gpio_keys_button babbage_buttons[] = {
{
.gpio = BABBAGE_POWER_KEY,
.code = BTN_0,
.desc = "PWR",
.active_low = 1,
.wakeup = 1,
},
};
static const struct gpio_keys_platform_data imx_button_data __initconst = {
.buttons = babbage_buttons,
.nbuttons = ARRAY_SIZE(babbage_buttons),
};
static struct pad_desc mx51babbage_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
@ -112,6 +131,22 @@ static struct pad_desc mx51babbage_pads[] = {
/* FEC PHY reset line */
MX51_PAD_EIM_A20__GPIO_2_14,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
MX51_PAD_SD2_CLK__SD2_CLK,
MX51_PAD_SD2_DATA0__SD2_DATA0,
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
};
/* Serial ports */
@ -281,13 +316,22 @@ __setup("otg_mode=", babbage_otg_mode);
static void __init mxc_board_init(void)
{
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
#endif
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
ARRAY_SIZE(mx51babbage_pads));
mxc_init_imx_uart();
babbage_fec_reset();
imx51_add_fec(NULL);
/* Set the PAD settings for the pwr key. */
power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
mxc_iomux_v3_setup_pad(&power_key);
imx51_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
@ -304,6 +348,9 @@ static void __init mxc_board_init(void)
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(&usbh1stp);
babbage_usbhub_reset();
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
}
static void __init mx51_babbage_timer_init(void)

22
arch/arm/mach-mx5/clock-mx51.c
View File

@ -362,7 +362,7 @@ static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static unsigned long clk_arm_get_rate(struct clk *clk)
static unsigned long clk_cpu_get_rate(struct clk *clk)
{
u32 cacrr, div;
unsigned long parent_rate;
@ -374,6 +374,22 @@ static unsigned long clk_arm_get_rate(struct clk *clk)
return parent_rate / div;
}
static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, cpu_podf;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
cpu_podf = parent_rate / rate - 1;
/* use post divider to change freq */
reg = __raw_readl(MXC_CCM_CACRR);
reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
__raw_writel(reg, MXC_CCM_CACRR);
return 0;
}
static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
@ -736,7 +752,8 @@ static struct clk periph_apm_clk = {
static struct clk cpu_clk = {
.parent = &pll1_sw_clk,
.get_rate = clk_arm_get_rate,
.get_rate = clk_cpu_get_rate,
.set_rate = clk_cpu_set_rate,
};
static struct clk ahb_clk = {
@ -1064,6 +1081,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
};
static void clk_tree_init(void)

29
arch/arm/mach-mx5/cpu_op-mx51.c Normal file
View File

@ -0,0 +1,29 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/types.h>
#include <mach/hardware.h>
#include <linux/kernel.h>
static struct cpu_op mx51_cpu_op[] = {
{
.cpu_rate = 160000000,},
{
.cpu_rate = 800000000,},
};
struct cpu_op *mx51_get_cpu_op(int *op)
{
*op = ARRAY_SIZE(mx51_cpu_op);
return mx51_cpu_op;
}

14
arch/arm/mach-mx5/cpu_op-mx51.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
extern struct cpu_op *mx51_get_cpu_op(int *op);

2
arch/arm/mach-mx5/devices-imx51.h
View File

@ -13,6 +13,8 @@ extern const struct imx_fec_data imx51_fec_data __initconst;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)

5
arch/arm/mach-omap1/devices.c
View File

@ -321,10 +321,9 @@ static struct platform_device omap_wdt_device = {
static int __init omap_init_wdt(void)
{
if (!cpu_is_omap16xx())
return;
return -ENODEV;
platform_device_register(&omap_wdt_device);
return 0;
return platform_device_register(&omap_wdt_device);
}
subsys_initcall(omap_init_wdt);
#endif

2
arch/arm/mach-omap1/include/mach/camera.h
View File

@ -1,6 +1,8 @@
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#include <media/omap1_camera.h>
void omap1_camera_init(void *);
static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info)

3
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -242,9 +242,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
devkit8000_vmmc1_supply.dev = mmc[0].dev;
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;

13
arch/arm/mach-omap2/omap4-common.c
View File

@ -44,6 +44,13 @@ void __init gic_init_irq(void)
}
#ifdef CONFIG_CACHE_L2X0
static void omap4_l2x0_disable(void)
{
/* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0);
}
static int __init omap_l2_cache_init(void)
{
/*
@ -70,6 +77,12 @@ static int __init omap_l2_cache_init(void)
else
l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
/*
* Override default outer_cache.disable with a OMAP4
* specific one
*/
outer_cache.disable = omap4_l2x0_disable;
return 0;
}
early_initcall(omap_l2_cache_init);

4
arch/arm/mach-orion5x/mpp.c
View File

@ -127,7 +127,7 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
/* Initialize gpiolib. */
orion_gpio_init();
while (mode->mpp >= 0) {
for ( ; mode->mpp >= 0; mode++) {
u32 *reg;
int num_type;
int shift;
@ -160,8 +160,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
orion_gpio_set_unused(mode->mpp);
orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
mode++;
}
writel(mpp_0_7_ctrl, MPP_0_7_CTRL);

2
arch/arm/mach-orion5x/ts78xx-setup.c
View File

@ -239,7 +239,7 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
static struct resource ts78xx_ts_nand_resources = {
.start = TS_NAND_DATA,
.end = TS_NAND_DATA + 4,
.flags = IORESOURCE_IO,
.flags = IORESOURCE_MEM,
};
static struct platform_device ts78xx_ts_nand_device = {

2
arch/arm/mach-pxa/cm-x2xx.c
View File

@ -476,8 +476,6 @@ static void __init cmx2xx_init(void)
static void __init cmx2xx_init_irq(void)
{
pxa27x_init_irq();
if (cpu_is_pxa25x()) {
pxa25x_init_irq();
cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);

2
arch/arm/mach-pxa/saar.c
View File

@ -116,7 +116,7 @@ static struct platform_device smc91x_device = {
},
};
#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE)
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static uint16_t lcd_power_on[] = {
/* single frame */
SMART_CMD_NOOP,

13
arch/arm/mach-s3c2410/h1940-bluetooth.c
View File

@ -30,7 +30,7 @@ static void h1940bt_enable(int on)
{
if (on) {
/* Power on the chip */
h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
/* Reset the chip */
mdelay(10);
@ -43,7 +43,7 @@ static void h1940bt_enable(int on)
mdelay(10);
gpio_set_value(S3C2410_GPH(1), 0);
mdelay(10);
h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
}
}
@ -64,7 +64,14 @@ static int __devinit h1940bt_probe(struct platform_device *pdev)
ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
if (ret) {
dev_err(&pdev->dev, "could not get GPH1\n");\
dev_err(&pdev->dev, "could not get GPH1\n");
return ret;
}
ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
if (ret) {
gpio_free(S3C2410_GPH(1));
dev_err(&pdev->dev, "could not get BT_POWER\n");
return ret;
}

10
arch/arm/mach-s3c2410/include/mach/gpio.h
View File

@ -22,6 +22,8 @@
#ifdef CONFIG_CPU_S3C244X
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
#else
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#endif
@ -30,8 +32,10 @@
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
#ifdef CONFIG_CPU_S3C24XX
#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
#ifdef CONFIG_CPU_S3C244X
#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
#else
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
#endif

57
arch/arm/mach-s3c2410/include/mach/h1940-latch.h
View File

@ -14,51 +14,30 @@
#ifndef __ASM_ARCH_H1940_LATCH_H
#define __ASM_ARCH_H1940_LATCH_H
#include <mach/gpio.h>
#ifndef __ASSEMBLY__
#define H1940_LATCH ((void __force __iomem *)0xF8000000)
#else
#define H1940_LATCH 0xF8000000
#endif
#define H1940_PA_LATCH (S3C2410_CS2)
#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
/* SD layer latch */
#define H1940_LATCH_SDQ1 (1<<16)
#define H1940_LATCH_LCD_P1 (1<<17)
#define H1940_LATCH_LCD_P2 (1<<18)
#define H1940_LATCH_LCD_P3 (1<<19)
#define H1940_LATCH_MAX1698_nSHUTDOWN (1<<20) /* LCD backlight */
#define H1940_LATCH_LED_RED (1<<21)
#define H1940_LATCH_SDQ7 (1<<22)
#define H1940_LATCH_USB_DP (1<<23)
#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
/* CPU layer latch */
#define H1940_LATCH_UDA_POWER (1<<24)
#define H1940_LATCH_AUDIO_POWER (1<<25)
#define H1940_LATCH_SM803_ENABLE (1<<26)
#define H1940_LATCH_LCD_P4 (1<<27)
#define H1940_LATCH_CPUQ5 (1<<28) /* untraced */
#define H1940_LATCH_BLUETOOTH_POWER (1<<29) /* active high */
#define H1940_LATCH_LED_GREEN (1<<30)
#define H1940_LATCH_LED_FLASH (1<<31)
/* default settings */
#define H1940_LATCH_DEFAULT \
H1940_LATCH_LCD_P4 | \
H1940_LATCH_SM803_ENABLE | \
H1940_LATCH_SDQ1 | \
H1940_LATCH_LCD_P1 | \
H1940_LATCH_LCD_P2 | \
H1940_LATCH_LCD_P3 | \
H1940_LATCH_MAX1698_nSHUTDOWN | \
H1940_LATCH_CPUQ5
/* control functions */
extern void h1940_latch_control(unsigned int clear, unsigned int set);
#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
#endif /* __ASM_ARCH_H1940_LATCH_H */

2
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
View File

@ -118,6 +118,8 @@
#define S3C2443_SCLKCON_UARTCLK (1<<8)
#define S3C2443_SCLKCON_USBHOST (1<<1)
#define S3C2443_PWRCFG_SLEEP (1<<15)
#include <asm/div64.h>
static inline unsigned int

2
arch/arm/mach-s3c2410/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xE0000000UL
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

169
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pwm_backlight.h>
#include <linux/i2c.h>
#include <video/platform_lcd.h>
#include <linux/mmc/host.h>
@ -59,6 +60,14 @@
#include <plat/mci.h>
#include <plat/ts.h>
#include <sound/uda1380.h>
#define H1940_LATCH ((void __force __iomem *)0xF8000000)
#define H1940_PA_LATCH S3C2410_CS2
#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
static struct map_desc h1940_iodesc[] __initdata = {
[0] = {
.virtual = (unsigned long)H1940_LATCH,
@ -100,9 +109,9 @@ static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
/* Board control latch control */
static unsigned int latch_state = H1940_LATCH_DEFAULT;
static unsigned int latch_state;
void h1940_latch_control(unsigned int clear, unsigned int set)
static void h1940_latch_control(unsigned int clear, unsigned int set)
{
unsigned long flags;
@ -116,7 +125,42 @@ void h1940_latch_control(unsigned int clear, unsigned int set)
local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(h1940_latch_control);
static inline int h1940_gpiolib_to_latch(int offset)
{
return 1 << (offset + 16);
}
static void h1940_gpiolib_latch_set(struct gpio_chip *chip,
unsigned offset, int value)
{
int latch_bit = h1940_gpiolib_to_latch(offset);
h1940_latch_control(value ? 0 : latch_bit,
value ? latch_bit : 0);
}
static int h1940_gpiolib_latch_output(struct gpio_chip *chip,
unsigned offset, int value)
{
h1940_gpiolib_latch_set(chip, offset, value);
return 0;
}
static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
unsigned offset)
{
return (latch_state >> (offset + 16)) & 1;
}
struct gpio_chip h1940_latch_gpiochip = {
.base = H1940_LATCH_GPIO(0),
.owner = THIS_MODULE,
.label = "H1940_LATCH",
.ngpio = 16,
.direction_output = h1940_gpiolib_latch_output,
.set = h1940_gpiolib_latch_set,
.get = h1940_gpiolib_latch_get,
};
static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
{
@ -125,10 +169,10 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
switch (cmd)
{
case S3C2410_UDC_P_ENABLE :
h1940_latch_control(0, H1940_LATCH_USB_DP);
gpio_set_value(H1940_LATCH_USB_DP, 1);
break;
case S3C2410_UDC_P_DISABLE :
h1940_latch_control(H1940_LATCH_USB_DP, 0);
gpio_set_value(H1940_LATCH_USB_DP, 0);
break;
case S3C2410_UDC_P_RESET :
break;
@ -199,10 +243,25 @@ static struct platform_device h1940_device_bluetooth = {
.id = -1,
};
static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
{
switch (power_mode) {
case MMC_POWER_OFF:
gpio_set_value(H1940_LATCH_SD_POWER, 0);
break;
case MMC_POWER_UP:
case MMC_POWER_ON:
gpio_set_value(H1940_LATCH_SD_POWER, 1);
break;
default:
break;
};
}
static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
.gpio_detect = S3C2410_GPF(5),
.gpio_wprotect = S3C2410_GPH(8),
.set_power = NULL,
.set_power = h1940_set_mmc_power,
.ocr_avail = MMC_VDD_32_33,
};
@ -213,15 +272,32 @@ static int h1940_backlight_init(struct device *dev)
gpio_direction_output(S3C2410_GPB(0), 0);
s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
return 0;
}
static int h1940_backlight_notify(struct device *dev, int brightness)
{
if (!brightness) {
gpio_direction_output(S3C2410_GPB(0), 1);
gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
} else {
gpio_direction_output(S3C2410_GPB(0), 0);
s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
}
return brightness;
}
static void h1940_backlight_exit(struct device *dev)
{
gpio_direction_output(S3C2410_GPB(0), 1);
gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
}
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
@ -229,6 +305,7 @@ static struct platform_pwm_backlight_data backlight_data = {
/* tcnt = 0x31 */
.pwm_period_ns = 36296,
.init = h1940_backlight_init,
.notify = h1940_backlight_notify,
.exit = h1940_backlight_exit,
};
@ -247,19 +324,37 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd,
int value;
if (!power) {
/* set to 3ec */
gpio_direction_output(S3C2410_GPC(0), 0);
gpio_set_value(S3C2410_GPC(0), 0);
/* wait for 3ac */
do {
value = gpio_get_value(S3C2410_GPC(6));
} while (value);
/* set to 38c */
gpio_direction_output(S3C2410_GPC(5), 0);
gpio_set_value(H1940_LATCH_LCD_P2, 0);
gpio_set_value(H1940_LATCH_LCD_P3, 0);
gpio_set_value(H1940_LATCH_LCD_P4, 0);
gpio_direction_output(S3C2410_GPC(1), 0);
gpio_direction_output(S3C2410_GPC(4), 0);
gpio_set_value(H1940_LATCH_LCD_P1, 0);
gpio_set_value(H1940_LATCH_LCD_P0, 0);
gpio_set_value(S3C2410_GPC(5), 0);
} else {
/* Set to 3ac */
gpio_direction_output(S3C2410_GPC(5), 1);
/* Set to 3ad */
gpio_direction_output(S3C2410_GPC(0), 1);
gpio_set_value(H1940_LATCH_LCD_P0, 1);
gpio_set_value(H1940_LATCH_LCD_P1, 1);
s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2));
gpio_set_value(S3C2410_GPC(5), 1);
gpio_set_value(S3C2410_GPC(0), 1);
gpio_set_value(H1940_LATCH_LCD_P3, 1);
gpio_set_value(H1940_LATCH_LCD_P2, 1);
gpio_set_value(H1940_LATCH_LCD_P4, 1);
}
}
@ -273,12 +368,26 @@ static struct platform_device h1940_lcd_powerdev = {
.dev.platform_data = &h1940_lcd_power_data,
};
static struct uda1380_platform_data uda1380_info = {
.gpio_power = H1940_LATCH_UDA_POWER,
.gpio_reset = S3C2410_GPA(12),
.dac_clk = UDA1380_DAC_CLK_SYSCLK,
};
static struct i2c_board_info h1940_i2c_devices[] = {
{
I2C_BOARD_INFO("uda1380", 0x1a),
.platform_data = &uda1380_info,
},
};
static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_ohci,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_pcm,
&s3c_device_usbgadget,
&h1940_device_leds,
&h1940_device_bluetooth,
@ -303,6 +412,10 @@ static void __init h1940_map_io(void)
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
s3c_pm_init();
/* Add latch gpio chip, set latch initial value */
h1940_latch_control(0, 0);
WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
}
/* H1940 and RX3715 need to reserve this for suspend */
@ -340,12 +453,38 @@ static void __init h1940_init(void)
writel(tmp, S3C2410_UPLLCON);
gpio_request(S3C2410_GPC(0), "LCD power");
gpio_request(S3C2410_GPC(1), "LCD power");
gpio_request(S3C2410_GPC(4), "LCD power");
gpio_request(S3C2410_GPC(5), "LCD power");
gpio_request(S3C2410_GPC(6), "LCD power");
gpio_request(H1940_LATCH_LCD_P0, "LCD power");
gpio_request(H1940_LATCH_LCD_P1, "LCD power");
gpio_request(H1940_LATCH_LCD_P2, "LCD power");
gpio_request(H1940_LATCH_LCD_P3, "LCD power");
gpio_request(H1940_LATCH_LCD_P4, "LCD power");
gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power");
gpio_direction_output(S3C2410_GPC(0), 0);
gpio_direction_output(S3C2410_GPC(1), 0);
gpio_direction_output(S3C2410_GPC(4), 0);
gpio_direction_output(S3C2410_GPC(5), 0);
gpio_direction_input(S3C2410_GPC(6));
gpio_direction_output(H1940_LATCH_LCD_P0, 0);
gpio_direction_output(H1940_LATCH_LCD_P1, 0);
gpio_direction_output(H1940_LATCH_LCD_P2, 0);
gpio_direction_output(H1940_LATCH_LCD_P3, 0);
gpio_direction_output(H1940_LATCH_LCD_P4, 0);
gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
gpio_request(H1940_LATCH_USB_DP, "USB pullup");
gpio_direction_output(H1940_LATCH_USB_DP, 0);
gpio_request(H1940_LATCH_SD_POWER, "SD power");
gpio_direction_output(H1940_LATCH_SD_POWER, 0);
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
i2c_register_board_info(0, h1940_i2c_devices,
ARRAY_SIZE(h1940_i2c_devices));
}
MACHINE_START(H1940, "IPAQ-H1940")

3
arch/arm/mach-s3c2412/s3c2412.c
View File

@ -51,6 +51,7 @@
#include <plat/clock.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@ -92,7 +93,7 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
/* rename devices that are s3c2412/s3c2413 specific */
s3c_device_sdi.name = "s3c2412-sdi";
s3c_device_lcd.name = "s3c2412-lcd";
s3c_device_nand.name = "s3c2412-nand";
s3c_nand_setname("s3c2412-nand");
/* alter IRQ of SDI controller */

6
arch/arm/mach-s3c2416/Kconfig
View File

@ -25,6 +25,11 @@ config S3C2416_DMA
help
Internal config node for S3C2416 DMA support
config S3C2416_PM
bool
help
Internal config node to apply S3C2416 power management
menu "S3C2416 Machines"
config MACH_SMDK2416
@ -33,6 +38,7 @@ config MACH_SMDK2416
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C2416_PM if PM
help
Say Y here if you are using an SMDK2416

2
arch/arm/mach-s3c2416/Makefile
View File

@ -11,7 +11,7 @@ obj- :=
obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
obj-$(CONFIG_CPU_S3C2416) += irq.o
obj-$(CONFIG_S3C2416_PM) += pm.o
#obj-$(CONFIG_S3C2416_DMA) += dma.o
# Machine support

2
arch/arm/mach-s3c2416/irq.c
View File

@ -243,6 +243,8 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev)
static struct sysdev_driver s3c2416_irq_driver = {
.add = s3c2416_irq_add,
.suspend = s3c24xx_irq_suspend,
.resume = s3c24xx_irq_resume,
};
static int __init s3c2416_irq_init(void)

84
arch/arm/mach-s3c2416/pm.c Normal file
View File

@ -0,0 +1,84 @@
/* linux/arch/arm/mach-s3c2416/pm.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S3C2416 - PM support (Based on Ben Dooks' S3C2412 PM support)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sysdev.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <mach/regs-power.h>
#include <mach/regs-s3c2443-clock.h>
#include <plat/cpu.h>
#include <plat/pm.h>
extern void s3c2412_sleep_enter(void);
static void s3c2416_cpu_suspend(void)
{
flush_cache_all();
/* enable wakeup sources regardless of battery state */
__raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
/* set the mode as sleep, 2BED represents "Go to BED" */
__raw_writel(0x2BED, S3C2443_PWRMODE);
s3c2412_sleep_enter();
}
static void s3c2416_pm_prepare(void)
{
/*
* write the magic value u-boot uses to check for resume into
* the INFORM0 register, and ensure INFORM1 is set to the
* correct address to resume from.
*/
__raw_writel(0x2BED, S3C2412_INFORM0);
__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
}
static int s3c2416_pm_add(struct sys_device *sysdev)
{
pm_cpu_prep = s3c2416_pm_prepare;
pm_cpu_sleep = s3c2416_cpu_suspend;
return 0;
}
static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state)
{
return 0;
}
static int s3c2416_pm_resume(struct sys_device *dev)
{
/* unset the return-from-sleep amd inform flags */
__raw_writel(0x0, S3C2443_PWRMODE);
__raw_writel(0x0, S3C2412_INFORM0);
__raw_writel(0x0, S3C2412_INFORM1);
return 0;
}
static struct sysdev_driver s3c2416_pm_driver = {
.add = s3c2416_pm_add,
.suspend = s3c2416_pm_suspend,
.resume = s3c2416_pm_resume,
};
static __init int s3c2416_pm_init(void)
{
return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
}
arch_initcall(s3c2416_pm_init);

3
arch/arm/mach-s3c2416/s3c2416.c
View File

@ -56,6 +56,7 @@
#include <plat/iic-core.h>
#include <plat/fb-core.h>
#include <plat/nand-core.h>
static struct map_desc s3c2416_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
@ -100,7 +101,7 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
s3c_device_nand.name = "s3c2416-nand";
s3c_nand_setname("s3c2412-nand");
}
/* s3c2416_map_io

7
arch/arm/mach-s3c2440/Kconfig
View File

@ -4,7 +4,6 @@
config CPU_S3C2440
bool
depends on ARCH_S3C2410
select CPU_ARM920T
select S3C_GPIO_PULL_UP
select S3C2410_CLOCK
@ -18,7 +17,6 @@ config CPU_S3C2440
config CPU_S3C2442
bool
depends on ARCH_S3C2410
select CPU_ARM920T
select S3C2410_CLOCK
select S3C2410_GPIO
@ -30,7 +28,7 @@ config CPU_S3C2442
config CPU_S3C244X
bool
depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
depends on CPU_S3C2440 || CPU_S3C2442
help
Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
@ -72,7 +70,7 @@ config S3C2440_PLL_16934400
config S3C2440_DMA
bool
depends on ARCH_S3C2410 && CPU_S3C24405B
depends on CPU_S3C2440
help
Support for S3C2440 specific DMA code5A
@ -181,7 +179,6 @@ config MACH_MINI2440
select CPU_S3C2440
select EEPROM_AT24
select LEDS_TRIGGER_BACKLIGHT
select SND_S3C24XX_SOC_S3C24XX_UDA134X
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
help

218
arch/arm/mach-s3c2440/mach-rx1950.c
View File

@ -25,8 +25,12 @@
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/sysdev.h>
#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <linux/pwm.h>
#include <linux/s3c_adc_battery.h>
#include <linux/leds.h>
#include <linux/i2c.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -55,6 +59,8 @@
#include <plat/irq.h>
#include <plat/ts.h>
#include <sound/uda1380.h>
#define LCD_PWM_PERIOD 192960
#define LCD_PWM_DUTY 127353
@ -127,6 +133,193 @@ static struct s3c2410fb_display rx1950_display = {
};
static int power_supply_init(struct device *dev)
{
return gpio_request(S3C2410_GPF(2), "cable plugged");
}
static int rx1950_is_ac_online(void)
{
return !gpio_get_value(S3C2410_GPF(2));
}
static void power_supply_exit(struct device *dev)
{
gpio_free(S3C2410_GPF(2));
}
static char *rx1950_supplicants[] = {
"main-battery"
};
static struct pda_power_pdata power_supply_info = {
.init = power_supply_init,
.is_ac_online = rx1950_is_ac_online,
.exit = power_supply_exit,
.supplied_to = rx1950_supplicants,
.num_supplicants = ARRAY_SIZE(rx1950_supplicants),
};
static struct resource power_supply_resources[] = {
[0] = {
.name = "ac",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
IORESOURCE_IRQ_HIGHEDGE,
.start = IRQ_EINT2,
.end = IRQ_EINT2,
},
};
static struct platform_device power_supply = {
.name = "pda-power",
.id = -1,
.dev = {
.platform_data =
&power_supply_info,
},
.resource = power_supply_resources,
.num_resources = ARRAY_SIZE(power_supply_resources),
};
static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
{ .volt = 4100, .cur = 156, .level = 100},
{ .volt = 4050, .cur = 156, .level = 95},
{ .volt = 4025, .cur = 141, .level = 90},
{ .volt = 3995, .cur = 144, .level = 85},
{ .volt = 3957, .cur = 162, .level = 80},
{ .volt = 3931, .cur = 147, .level = 75},
{ .volt = 3902, .cur = 147, .level = 70},
{ .volt = 3863, .cur = 153, .level = 65},
{ .volt = 3838, .cur = 150, .level = 60},
{ .volt = 3800, .cur = 153, .level = 55},
{ .volt = 3765, .cur = 153, .level = 50},
{ .volt = 3748, .cur = 172, .level = 45},
{ .volt = 3740, .cur = 153, .level = 40},
{ .volt = 3714, .cur = 175, .level = 35},
{ .volt = 3710, .cur = 156, .level = 30},
{ .volt = 3963, .cur = 156, .level = 25},
{ .volt = 3672, .cur = 178, .level = 20},
{ .volt = 3651, .cur = 178, .level = 15},
{ .volt = 3629, .cur = 178, .level = 10},
{ .volt = 3612, .cur = 162, .level = 5},
{ .volt = 3605, .cur = 162, .level = 0},
};
static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
{ .volt = 4200, .cur = 0, .level = 100},
{ .volt = 4190, .cur = 0, .level = 99},
{ .volt = 4178, .cur = 0, .level = 95},
{ .volt = 4110, .cur = 0, .level = 70},
{ .volt = 4076, .cur = 0, .level = 65},
{ .volt = 4046, .cur = 0, .level = 60},
{ .volt = 4021, .cur = 0, .level = 55},
{ .volt = 3999, .cur = 0, .level = 50},
{ .volt = 3982, .cur = 0, .level = 45},
{ .volt = 3965, .cur = 0, .level = 40},
{ .volt = 3957, .cur = 0, .level = 35},
{ .volt = 3948, .cur = 0, .level = 30},
{ .volt = 3936, .cur = 0, .level = 25},
{ .volt = 3927, .cur = 0, .level = 20},
{ .volt = 3906, .cur = 0, .level = 15},
{ .volt = 3880, .cur = 0, .level = 10},
{ .volt = 3829, .cur = 0, .level = 5},
{ .volt = 3820, .cur = 0, .level = 0},
};
int rx1950_bat_init(void)
{
int ret;
ret = gpio_request(S3C2410_GPJ(2), "rx1950-charger-enable-1");
if (ret)
goto err_gpio1;
ret = gpio_request(S3C2410_GPJ(3), "rx1950-charger-enable-2");
if (ret)
goto err_gpio2;
return 0;
err_gpio2:
gpio_free(S3C2410_GPJ(2));
err_gpio1:
return ret;
}
void rx1950_bat_exit(void)
{
gpio_free(S3C2410_GPJ(2));
gpio_free(S3C2410_GPJ(3));
}
void rx1950_enable_charger(void)
{
gpio_direction_output(S3C2410_GPJ(2), 1);
gpio_direction_output(S3C2410_GPJ(3), 1);
}
void rx1950_disable_charger(void)
{
gpio_direction_output(S3C2410_GPJ(2), 0);
gpio_direction_output(S3C2410_GPJ(3), 0);
}
static struct gpio_led rx1950_leds_desc[] = {
{
.name = "Green",
.default_trigger = "main-battery-charging-or-full",
.gpio = S3C2410_GPA(6),
},
{
.name = "Red",
.default_trigger = "main-battery-full",
.gpio = S3C2410_GPA(7),
},
{
.name = "Blue",
.default_trigger = "rx1950-acx-mem",
.gpio = S3C2410_GPA(11),
},
};
static struct gpio_led_platform_data rx1950_leds_pdata = {
.num_leds = ARRAY_SIZE(rx1950_leds_desc),
.leds = rx1950_leds_desc,
};
static struct platform_device rx1950_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &rx1950_leds_pdata,
},
};
static struct s3c_adc_bat_pdata rx1950_bat_cfg = {
.init = rx1950_bat_init,
.exit = rx1950_bat_exit,
.enable_charger = rx1950_enable_charger,
.disable_charger = rx1950_disable_charger,
.gpio_charge_finished = S3C2410_GPF(3),
.lut_noac = bat_lut_noac,
.lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
.lut_acin = bat_lut_acin,
.lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
.volt_channel = 0,
.current_channel = 1,
.volt_mult = 4235,
.current_mult = 2900,
.internal_impedance = 200,
};
static struct platform_device rx1950_battery = {
.name = "s3c-adc-battery",
.id = -1,
.dev = {
.parent = &s3c_device_adc.dev,
.platform_data = &rx1950_bat_cfg,
},
};
static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
.displays = &rx1950_display,
.num_displays = 1,
@ -481,11 +674,17 @@ static struct platform_device rx1950_device_gpiokeys = {
.dev.platform_data = &rx1950_gpio_keys_data,
};
static struct s3c2410_platform_i2c rx1950_i2c_data = {
.flags = 0,
.slave_addr = 0x42,
.frequency = 400 * 1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
static struct uda1380_platform_data uda1380_info = {
.gpio_power = S3C2410_GPJ(0),
.gpio_reset = S3C2410_GPD(0),
.dac_clk = UDA1380_DAC_CLK_SYSCLK,
};
static struct i2c_board_info rx1950_i2c_devices[] = {
{
I2C_BOARD_INFO("uda1380", 0x1a),
.platform_data = &uda1380_info,
},
};
static struct platform_device *rx1950_devices[] __initdata = {
@ -493,6 +692,7 @@ static struct platform_device *rx1950_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_pcm,
&s3c_device_usbgadget,
&s3c_device_rtc,
&s3c_device_nand,
@ -503,6 +703,9 @@ static struct platform_device *rx1950_devices[] __initdata = {
&s3c_device_timer[1],
&rx1950_backlight,
&rx1950_device_gpiokeys,
&power_supply,
&rx1950_battery,
&rx1950_leds,
};
static struct clk *rx1950_clocks[] __initdata = {
@ -538,7 +741,7 @@ static void __init rx1950_init_machine(void)
s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
s3c_i2c0_set_platdata(&rx1950_i2c_data);
s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&rx1950_nand_info);
/* Turn off suspend on both USB ports, and switch the
@ -569,6 +772,9 @@ static void __init rx1950_init_machine(void)
WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
i2c_register_board_info(0, rx1950_i2c_devices,
ARRAY_SIZE(rx1950_i2c_devices));
}
/* H1940 and RX3715 need to reserve this for suspend */

3
arch/arm/mach-s3c2440/s3c244x.c
View File

@ -44,6 +44,7 @@
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
@ -68,7 +69,7 @@ void __init s3c244x_map_io(void)
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_i2c0.name = "s3c2440-i2c";
s3c_device_nand.name = "s3c2440-nand";
s3c_nand_setname("s3c2440-nand");
s3c_device_ts.name = "s3c2440-ts";
s3c_device_usbgadget.name = "s3c2440-usbgadget";
}

3
arch/arm/mach-s3c2443/s3c2443.c
View File

@ -36,6 +36,7 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/fb-core.h>
#include <plat/nand-core.h>
static struct map_desc s3c2443_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
@ -62,7 +63,7 @@ int __init s3c2443_init(void)
s3c24xx_reset_hook = s3c2443_hard_reset;
s3c_device_nand.name = "s3c2412-nand";
s3c_nand_setname("s3c2412-nand");
s3c_fb_setname("s3c2443-fb");
/* change WDT IRQ number */

2
arch/arm/mach-s3c24a0/include/mach/vmalloc.h
View File

@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xe0000000UL)
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

23
arch/arm/mach-s3c64xx/Kconfig
View File

@ -98,12 +98,33 @@ config MACH_ANW6410
help
Machine support for the A&W6410
config MACH_MINI6410
bool "MINI6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C64XX_SETUP_SDHCI
select S3C_DEV_USB_HOST
select S3C_DEV_NAND
select S3C_DEV_FB
select S3C64XX_SETUP_FB_24BPP
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_TS
help
Machine support for the FriendlyARM MINI6410
config MACH_REAL6410
bool "REAL6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C64XX_SETUP_SDHCI
select S3C_DEV_FB
select S3C64XX_SETUP_FB_24BPP
select S3C_DEV_NAND
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_TS
select S3C_DEV_USB_HOST
help
Machine support for the CoreWind REAL6410
@ -122,7 +143,7 @@ config MACH_SMDK6410
select S3C_DEV_USB_HSOTG
select S3C_DEV_WDT
select SAMSUNG_DEV_KEYPAD
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_IDE

1
arch/arm/mach-s3c64xx/Makefile
View File

@ -53,6 +53,7 @@ obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o

63
arch/arm/mach-s3c64xx/dev-audio.c
View File

@ -22,27 +22,16 @@
#include <plat/audio.h>
#include <plat/gpio-cfg.h>
#include <mach/gpio-bank-c.h>
#include <mach/gpio-bank-d.h>
#include <mach/gpio-bank-e.h>
#include <mach/gpio-bank-h.h>
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
base = S3C64XX_GPD(0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
@ -50,18 +39,17 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
}
@ -170,20 +158,14 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4);
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
base = S3C64XX_GPD(0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
@ -191,6 +173,7 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
@ -264,24 +247,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1);
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
return 0;
return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
}
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
return 0;
return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s3c64xx_ac97_resource[] = {

8
arch/arm/mach-s3c64xx/gpiolib.c
View File

@ -195,11 +195,6 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.get_pull = s3c_gpio_getpull_updown,
};
int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
{
return IRQ_EINT(0) + pin;
}
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
@ -227,12 +222,13 @@ static struct s3c_gpio_chip gpio_2bit[] = {
},
}, {
.base = S3C64XX_GPN_BASE,
.irq_base = IRQ_EINT(0),
.config = &gpio_2bit_cfg_eint10,
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
.to_irq = s3c64xx_gpio2int_gpn,
.to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = S3C64XX_GPO_BASE,

2
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xE0000000UL
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

357
arch/arm/mach-s3c64xx/mach-mini6410.c Normal file
View File

@ -0,0 +1,357 @@
/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
*
* Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/dm9000.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/serial_core.h>
#include <linux/types.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <mach/s3c6410.h>
#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
#include <video/platform_lcd.h>
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
};
/* DM9000AEP 10/100 ethernet controller */
static struct resource mini6410_dm9k_resource[] = {
[0] = {
.start = S3C64XX_PA_XM0CSN1,
.end = S3C64XX_PA_XM0CSN1 + 1,
.flags = IORESOURCE_MEM
},
[1] = {
.start = S3C64XX_PA_XM0CSN1 + 4,
.end = S3C64XX_PA_XM0CSN1 + 5,
.flags = IORESOURCE_MEM
},
[2] = {
.start = S3C_EINT(7),
.end = S3C_EINT(7),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
}
};
static struct dm9000_plat_data mini6410_dm9k_pdata = {
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
};
static struct platform_device mini6410_device_eth = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
.resource = mini6410_dm9k_resource,
.dev = {
.platform_data = &mini6410_dm9k_pdata,
},
};
static struct mtd_partition mini6410_nand_part[] = {
[0] = {
.name = "uboot",
.size = SZ_1M,
.offset = 0,
},
[1] = {
.name = "kernel",
.size = SZ_2M,
.offset = SZ_1M,
},
[2] = {
.name = "rootfs",
.size = MTDPART_SIZ_FULL,
.offset = SZ_1M + SZ_2M,
},
};
static struct s3c2410_nand_set mini6410_nand_sets[] = {
[0] = {
.name = "nand",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(mini6410_nand_part),
.partitions = mini6410_nand_part,
},
};
static struct s3c2410_platform_nand mini6410_nand_info = {
.tacls = 25,
.twrph0 = 55,
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
.sets = mini6410_nand_sets,
};
static struct s3c_fb_pd_win mini6410_fb_win[] = {
{
.win_mode = { /* 4.3" 480x272 */
.left_margin = 3,
.right_margin = 2,
.upper_margin = 1,
.lower_margin = 1,
.hsync_len = 40,
.vsync_len = 1,
.xres = 480,
.yres = 272,
},
.max_bpp = 32,
.default_bpp = 16,
}, {
.win_mode = { /* 7.0" 800x480 */
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
},
};
static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &mini6410_fb_win[0],
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(S3C64XX_GPE(0), 1);
else
gpio_direction_output(S3C64XX_GPE(0), 0);
}
static struct plat_lcd_data mini6410_lcd_power_data = {
.set_power = mini6410_lcd_power_set,
};
static struct platform_device mini6410_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &mini6410_lcd_power_data,
};
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.delay = 10000,
.presc = 49,
.oversampling_shift = 2,
};
static struct platform_device *mini6410_devices[] __initdata = {
&mini6410_device_eth,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_ohci,
&s3c_device_nand,
&s3c_device_fb,
&mini6410_lcd_powerdev,
&s3c_device_adc,
&s3c_device_ts,
};
static void __init mini6410_map_io(void)
{
u32 tmp;
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
__raw_writel(tmp, S3C64XX_SPCON);
/* remove the LCD bypass */
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
tmp &= ~MIFPCON_LCD_BYPASS;
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}
/*
* mini6410_features string
*
* 0-9 LCD configuration
*
*/
static char mini6410_features_str[12] __initdata = "0";
static int __init mini6410_features_setup(char *str)
{
if (str)
strlcpy(mini6410_features_str, str,
sizeof(mini6410_features_str));
return 1;
}
__setup("mini6410=", mini6410_features_setup);
#define FEATURE_SCREEN (1 << 0)
struct mini6410_features_t {
int done;
int lcd_index;
};
static void mini6410_parse_features(
struct mini6410_features_t *features,
const char *features_str)
{
const char *fp = features_str;
features->done = 0;
features->lcd_index = 0;
while (*fp) {
char f = *fp++;
switch (f) {
case '0'...'9': /* tft screen */
if (features->done & FEATURE_SCREEN) {
printk(KERN_INFO "MINI6410: '%c' ignored, "
"screen type already set\n", f);
} else {
int li = f - '0';
if (li >= ARRAY_SIZE(mini6410_fb_win))
printk(KERN_INFO "MINI6410: '%c' out "
"of range LCD mode\n", f);
else {
features->lcd_index = li;
}
}
features->done |= FEATURE_SCREEN;
break;
}
}
}
static void __init mini6410_machine_init(void)
{
u32 cs1;
struct mini6410_features_t features = { 0 };
printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
mini6410_features_str);
/* Parse the feature string */
mini6410_parse_features(&features, mini6410_features_str);
mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
mini6410_lcd_pdata.win[0]->win_mode.xres,
mini6410_lcd_pdata.win[0]->win_mode.yres);
s3c_nand_set_platdata(&mini6410_nand_info);
s3c_fb_set_platdata(&mini6410_lcd_pdata);
s3c24xx_ts_set_platdata(&s3c_ts_platform);
/* configure nCS1 width to 16 bits */
cs1 = __raw_readl(S3C64XX_SROM_BW) &
~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
S3C64XX_SROM_BW__NCS1__SHIFT;
__raw_writel(cs1, S3C64XX_SROM_BW);
/* set timing for nCS1 suitable for ethernet chip */
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
gpio_request(S3C64XX_GPF(15), "LCD power");
gpio_request(S3C64XX_GPE(0), "LCD power");
platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
}
MACHINE_START(MINI6410, "MINI6410")
/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = mini6410_map_io,
.init_machine = mini6410_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END

200
arch/arm/mach-s3c64xx/mach-real6410.c
View File

@ -12,23 +12,39 @@
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/dm9000.h>
#include <linux/serial_core.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/types.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <mach/s3c6410.h>
#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <mach/s3c6410.h>
#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
#include <video/platform_lcd.h>
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@ -99,22 +115,192 @@ static struct platform_device real6410_device_eth = {
},
};
static struct s3c_fb_pd_win real6410_fb_win[] = {
{
.win_mode = { /* 4.3" 480x272 */
.left_margin = 3,
.right_margin = 2,
.upper_margin = 1,
.lower_margin = 1,
.hsync_len = 40,
.vsync_len = 1,
.xres = 480,
.yres = 272,
},
.max_bpp = 32,
.default_bpp = 16,
}, {
.win_mode = { /* 7.0" 800x480 */
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
},
};
static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &real6410_fb_win[0],
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct mtd_partition real6410_nand_part[] = {
[0] = {
.name = "uboot",
.size = SZ_1M,
.offset = 0,
},
[1] = {
.name = "kernel",
.size = SZ_2M,
.offset = SZ_1M,
},
[2] = {
.name = "rootfs",
.size = MTDPART_SIZ_FULL,
.offset = SZ_1M + SZ_2M,
},
};
static struct s3c2410_nand_set real6410_nand_sets[] = {
[0] = {
.name = "nand",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(real6410_nand_part),
.partitions = real6410_nand_part,
},
};
static struct s3c2410_platform_nand real6410_nand_info = {
.tacls = 25,
.twrph0 = 55,
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(real6410_nand_sets),
.sets = real6410_nand_sets,
};
static struct platform_device *real6410_devices[] __initdata = {
&real6410_device_eth,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_fb,
&s3c_device_nand,
&s3c_device_adc,
&s3c_device_ts,
&s3c_device_ohci,
};
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.delay = 10000,
.presc = 49,
.oversampling_shift = 2,
};
static void __init real6410_map_io(void)
{
u32 tmp;
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
__raw_writel(tmp, S3C64XX_SPCON);
/* remove the LCD bypass */
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
tmp &= ~MIFPCON_LCD_BYPASS;
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}
/*
* real6410_features string
*
* 0-9 LCD configuration
*
*/
static char real6410_features_str[12] __initdata = "0";
static int __init real6410_features_setup(char *str)
{
if (str)
strlcpy(real6410_features_str, str,
sizeof(real6410_features_str));
return 1;
}
__setup("real6410=", real6410_features_setup);
#define FEATURE_SCREEN (1 << 0)
struct real6410_features_t {
int done;
int lcd_index;
};
static void real6410_parse_features(
struct real6410_features_t *features,
const char *features_str)
{
const char *fp = features_str;
features->done = 0;
features->lcd_index = 0;
while (*fp) {
char f = *fp++;
switch (f) {
case '0'...'9': /* tft screen */
if (features->done & FEATURE_SCREEN) {
printk(KERN_INFO "REAL6410: '%c' ignored, "
"screen type already set\n", f);
} else {
int li = f - '0';
if (li >= ARRAY_SIZE(real6410_fb_win))
printk(KERN_INFO "REAL6410: '%c' out "
"of range LCD mode\n", f);
else {
features->lcd_index = li;
}
}
features->done |= FEATURE_SCREEN;
break;
}
}
}
static void __init real6410_machine_init(void)
{
u32 cs1;
struct real6410_features_t features = { 0 };
printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
real6410_features_str);
/* Parse the feature string */
real6410_parse_features(&features, real6410_features_str);
real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
real6410_lcd_pdata.win[0]->win_mode.xres,
real6410_lcd_pdata.win[0]->win_mode.yres);
s3c_fb_set_platdata(&real6410_lcd_pdata);
s3c_nand_set_platdata(&real6410_nand_info);
s3c24xx_ts_set_platdata(&s3c_ts_platform);
/* configure nCS1 width to 16 bits */
@ -136,6 +322,8 @@ static void __init real6410_machine_init(void)
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
gpio_request(S3C64XX_GPF(15), "LCD power");
platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
}

13
arch/arm/mach-s3c64xx/setup-fb-24bpp.c
View File

@ -23,15 +23,6 @@
extern void s3c64xx_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
}

11
arch/arm/mach-s3c64xx/setup-ide.c
View File

@ -17,11 +17,11 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
#include <plat/ata.h>
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
u32 gpio = 0;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
@ -32,15 +32,12 @@ void s3c64xx_ide_setup_gpio(void)
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}

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