arm: plat-orion: use void __iomem pointers for addr-map functions
The functions for address mapping management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i)
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 8,
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.remappable_wins = 4,
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.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
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.bridge_virt_base = BRIDGE_VIRT_BASE,
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};
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static const struct __initdata orion_addr_map_info addr_map_info[] = {
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@ -41,7 +41,7 @@
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 8,
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.remappable_wins = 4,
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.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
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.bridge_virt_base = BRIDGE_VIRT_BASE,
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};
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static const struct __initdata orion_addr_map_info addr_map_info[] = {
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@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
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/*
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* Setup MBUS dram target info.
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*/
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orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU_BASE);
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}
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@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
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*/
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if (mv78xx0_core_index() == 0)
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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DDR_WINDOW_CPU0_BASE);
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(void __iomem *) DDR_WINDOW_CPU0_BASE);
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else
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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DDR_WINDOW_CPU1_BASE);
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(void __iomem *) DDR_WINDOW_CPU1_BASE);
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}
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void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
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static struct orion_addr_map_cfg addr_map_cfg __initdata = {
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.num_wins = 8,
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.cpu_win_can_remap = cpu_win_can_remap,
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.bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE,
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.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
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};
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static const struct __initdata orion_addr_map_info addr_map_info[] = {
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@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
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/*
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* Setup MBUS dram target info.
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*/
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orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
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}
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void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
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@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
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static void __init __iomem *
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orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
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return cfg->bridge_virt_base + (win << 4);
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}
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/*
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@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
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* Setup MBUS dram target info.
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*/
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void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
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const u32 ddr_window_cpu_base)
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const void __iomem *ddr_window_cpu_base)
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{
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void __iomem *addr;
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int i;
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int cs;
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orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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addr = (void __iomem *)ddr_window_cpu_base;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(addr + DDR_BASE_CS_OFF(i));
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u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
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u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
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/*
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* Chip select enabled?
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@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
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struct orion_addr_map_cfg {
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const int num_wins; /* Total number of windows */
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const int remappable_wins;
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const u32 bridge_virt_base;
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void __iomem * const bridge_virt_base;
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/* If NULL, the default cpu_win_can_remap will be used, using
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the value in remappable_wins */
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@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
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const u8 attr, const int remap);
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void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
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const u32 ddr_window_cpu_base);
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const void __iomem *ddr_window_cpu_base);
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#endif
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