e1000: add dynamic generic MSI interrupt routine
Add a generic MSI interrupt routine that is IO read-free, speeding up MSI interrupt handling. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
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04fedbfbc3
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@ -157,6 +157,9 @@ static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
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static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
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static int e1000_set_mac(struct net_device *netdev, void *p);
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static irqreturn_t e1000_intr(int irq, void *data);
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#ifdef CONFIG_PCI_MSI
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static irqreturn_t e1000_intr_msi(int irq, void *data);
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#endif
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static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
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struct e1000_tx_ring *tx_ring);
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#ifdef CONFIG_E1000_NAPI
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@ -288,7 +291,7 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
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flags = IRQF_SHARED;
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#ifdef CONFIG_PCI_MSI
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if (adapter->hw.mac_type > e1000_82547_rev_2) {
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if (adapter->hw.mac_type >= e1000_82571) {
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adapter->have_msi = TRUE;
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if ((err = pci_enable_msi(adapter->pdev))) {
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DPRINTK(PROBE, ERR,
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@ -296,8 +299,14 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
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adapter->have_msi = FALSE;
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}
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}
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if (adapter->have_msi)
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if (adapter->have_msi) {
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flags &= ~IRQF_SHARED;
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err = request_irq(adapter->pdev->irq, &e1000_intr_msi, flags,
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netdev->name, netdev);
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if (err)
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DPRINTK(PROBE, ERR,
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"Unable to allocate interrupt Error: %d\n", err);
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} else
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#endif
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if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
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netdev->name, netdev)))
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@ -3466,6 +3475,83 @@ e1000_update_stats(struct e1000_adapter *adapter)
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spin_unlock_irqrestore(&adapter->stats_lock, flags);
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}
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#ifdef CONFIG_PCI_MSI
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/**
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* e1000_intr_msi - Interrupt Handler
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* @irq: interrupt number
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* @data: pointer to a network interface device structure
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**/
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static
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irqreturn_t e1000_intr_msi(int irq, void *data)
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{
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struct net_device *netdev = data;
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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#ifndef CONFIG_E1000_NAPI
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int i;
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#endif
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/* this code avoids the read of ICR but has to get 1000 interrupts
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* at every link change event before it will notice the change */
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if (++adapter->detect_link >= 1000) {
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uint32_t icr = E1000_READ_REG(hw, ICR);
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#ifdef CONFIG_E1000_NAPI
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/* read ICR disables interrupts using IAM, so keep up with our
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* enable/disable accounting */
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atomic_inc(&adapter->irq_sem);
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#endif
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adapter->detect_link = 0;
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if ((icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) &&
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(icr & E1000_ICR_INT_ASSERTED)) {
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hw->get_link_status = 1;
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/* 80003ES2LAN workaround--
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* For packet buffer work-around on link down event;
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* disable receives here in the ISR and
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* reset adapter in watchdog
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*/
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if (netif_carrier_ok(netdev) &&
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(adapter->hw.mac_type == e1000_80003es2lan)) {
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/* disable receives */
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uint32_t rctl = E1000_READ_REG(hw, RCTL);
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E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
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}
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/* guard against interrupt when we're going down */
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if (!test_bit(__E1000_DOWN, &adapter->flags))
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mod_timer(&adapter->watchdog_timer,
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jiffies + 1);
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}
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} else {
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E1000_WRITE_REG(hw, ICR, (0xffffffff & ~(E1000_ICR_RXSEQ |
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E1000_ICR_LSC)));
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/* bummer we have to flush here, but things break otherwise as
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* some event appears to be lost or delayed and throughput
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* drops. In almost all tests this flush is un-necessary */
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E1000_WRITE_FLUSH(hw);
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#ifdef CONFIG_E1000_NAPI
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/* Interrupt Auto-Mask (IAM)...upon writing ICR, interrupts are
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* masked. No need for the IMC write, but it does mean we
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* should account for it ASAP. */
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atomic_inc(&adapter->irq_sem);
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#endif
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}
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#ifdef CONFIG_E1000_NAPI
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if (likely(netif_rx_schedule_prep(netdev)))
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__netif_rx_schedule(netdev);
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else
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e1000_irq_enable(adapter);
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#else
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for (i = 0; i < E1000_MAX_INTR; i++)
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if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
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!e1000_clean_tx_irq(adapter, adapter->tx_ring)))
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break;
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#endif
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return IRQ_HANDLED;
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}
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#endif
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/**
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* e1000_intr - Interrupt Handler
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