perf/x86/intel: Add Intel Skylake PMU support
Add perf core PMU support for future Intel Skylake CPU cores. The code is based on Haswell/Broadwell. There is a new cache event list, based on the updated Haswell event list. Skylake has removed most counter constraints on basic events, so the basic constraints table now only has a single entry (plus the fixed counters). TSX support and various other setups are all shared with Haswell. Skylake has 32 LBR entries. Add a new LBR init function to set this up. The filters are all the same as Haswell. It also has a new LBR format with a separate LBR_INFO_* MSR, but that has been already added earlier. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-7-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andi Kleen
Ingo Molnar
parent
425507fa5f
commit
9a92e16fd7
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@ -165,7 +165,7 @@ struct intel_excl_cntrs {
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unsigned core_id; /* per-core: core id */
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};
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#define MAX_LBR_ENTRIES 16
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#define MAX_LBR_ENTRIES 32
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enum {
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X86_PERF_KFREE_SHARED = 0,
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@ -861,6 +861,8 @@ extern struct event_constraint intel_ivb_pebs_event_constraints[];
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extern struct event_constraint intel_hsw_pebs_event_constraints[];
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extern struct event_constraint intel_skl_pebs_event_constraints[];
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struct event_constraint *intel_pebs_constraints(struct perf_event *event);
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void intel_pmu_pebs_enable(struct perf_event *event);
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@ -899,6 +901,8 @@ void intel_pmu_lbr_init_snb(void);
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void intel_pmu_lbr_init_hsw(void);
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void intel_pmu_lbr_init_skl(void);
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int intel_pmu_setup_lbr_filter(struct perf_event *event);
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void intel_pt_interrupt(void);
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@ -177,6 +177,14 @@ static struct event_constraint intel_slm_event_constraints[] __read_mostly =
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EVENT_CONSTRAINT_END
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};
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struct event_constraint intel_skl_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
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EVENT_CONSTRAINT_END
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};
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static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
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@ -193,6 +201,13 @@ static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
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EVENT_EXTRA_END
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};
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static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
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EVENT_EXTRA_END
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};
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EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
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EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
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EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
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@ -244,6 +259,200 @@ static u64 intel_pmu_event_map(int hw_event)
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return intel_perfmon_event_map[hw_event];
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}
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/*
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* Notes on the events:
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* - data reads do not include code reads (comparable to earlier tables)
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* - data counts include speculative execution (except L1 write, dtlb, bpu)
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* - remote node access includes remote memory, remote cache, remote mmio.
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* - prefetches are not included in the counts.
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* - icache miss does not include decoded icache
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*/
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#define SKL_DEMAND_DATA_RD BIT_ULL(0)
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#define SKL_DEMAND_RFO BIT_ULL(1)
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#define SKL_ANY_RESPONSE BIT_ULL(16)
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#define SKL_SUPPLIER_NONE BIT_ULL(17)
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#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
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#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
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#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
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#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
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#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
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SKL_L3_MISS_REMOTE_HOP0_DRAM| \
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SKL_L3_MISS_REMOTE_HOP1_DRAM| \
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SKL_L3_MISS_REMOTE_HOP2P_DRAM)
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#define SKL_SPL_HIT BIT_ULL(30)
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#define SKL_SNOOP_NONE BIT_ULL(31)
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#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
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#define SKL_SNOOP_MISS BIT_ULL(33)
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#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
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#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
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#define SKL_SNOOP_HITM BIT_ULL(36)
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#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
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#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
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SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
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SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
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SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
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#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
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#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
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SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
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SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
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SKL_SNOOP_HITM|SKL_SPL_HIT)
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#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
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#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
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#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
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SKL_L3_MISS_REMOTE_HOP1_DRAM| \
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SKL_L3_MISS_REMOTE_HOP2P_DRAM)
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static __initconst const u64 skl_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
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[ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
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[ C(RESULT_MISS) ] = 0x0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
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[ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
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[ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
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[ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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};
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static __initconst const u64 skl_hw_cache_extra_regs
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
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SKL_LLC_ACCESS|SKL_ANY_SNOOP,
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[ C(RESULT_MISS) ] = SKL_DEMAND_READ|
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SKL_L3_MISS|SKL_ANY_SNOOP|
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SKL_SUPPLIER_NONE,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
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SKL_LLC_ACCESS|SKL_ANY_SNOOP,
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[ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
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SKL_L3_MISS|SKL_ANY_SNOOP|
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SKL_SUPPLIER_NONE,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
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SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
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[ C(RESULT_MISS) ] = SKL_DEMAND_READ|
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SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
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SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
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[ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
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SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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};
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#define SNB_DMND_DATA_RD (1ULL << 0)
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#define SNB_DMND_RFO (1ULL << 1)
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#define SNB_DMND_IFETCH (1ULL << 2)
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@ -3278,6 +3487,29 @@ __init int intel_pmu_init(void)
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pr_cont("Broadwell events, ");
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break;
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case 78: /* 14nm Skylake Mobile */
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case 94: /* 14nm Skylake Desktop */
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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intel_pmu_lbr_init_skl();
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x86_pmu.event_constraints = intel_skl_event_constraints;
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x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
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x86_pmu.extra_regs = intel_skl_extra_regs;
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x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
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/* all extra regs are per-cpu when HT is on */
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
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x86_pmu.hw_config = hsw_hw_config;
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x86_pmu.get_event_constraints = hsw_get_event_constraints;
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x86_pmu.cpu_events = hsw_events_attrs;
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WARN_ON(!x86_pmu.format_attrs);
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x86_pmu.cpu_events = hsw_events_attrs;
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pr_cont("Skylake events, ");
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break;
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default:
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switch (x86_pmu.version) {
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case 1:
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@ -688,6 +688,28 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = {
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EVENT_CONSTRAINT_END
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};
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struct event_constraint intel_skl_pebs_event_constraints[] = {
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INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
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EVENT_CONSTRAINT_END
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};
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struct event_constraint *intel_pebs_constraints(struct perf_event *event)
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{
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struct event_constraint *c;
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@ -973,6 +973,26 @@ void intel_pmu_lbr_init_hsw(void)
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pr_cont("16-deep LBR, ");
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}
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/* skylake */
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__init void intel_pmu_lbr_init_skl(void)
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{
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x86_pmu.lbr_nr = 32;
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x86_pmu.lbr_tos = MSR_LBR_TOS;
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x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
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x86_pmu.lbr_to = MSR_LBR_NHM_TO;
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x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
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x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
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/*
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* SW branch filter usage:
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* - support syscall, sysret capture.
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* That requires LBR_FAR but that means far
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* jmp need to be filtered out
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*/
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pr_cont("32-deep LBR, ");
|
||||
}
|
||||
|
||||
/* atom */
|
||||
void __init intel_pmu_lbr_init_atom(void)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue