libata: convert ata_pci_init_native_mode() users to new init model
Convert drivers which use ata_pci_init_native_mode() to new init model. ata_pci_init_native_host() is used instead. sata_nv, sata_uli and sata_sis are in this category. Tested on nVidia Corporation CK804 Serial ATA Controller [10de:0054] in both BMDMA and ADMA mode. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Tejun Heo
Jeff Garzik
parent
eca25dca17
commit
9a829ccfc8
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@ -369,7 +369,6 @@ static const struct ata_port_operations nv_generic_ops = {
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_data_xfer,
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.irq_handler = nv_generic_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -396,7 +395,6 @@ static const struct ata_port_operations nv_nf2_ops = {
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_data_xfer,
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.irq_handler = nv_nf2_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -423,7 +421,6 @@ static const struct ata_port_operations nv_ck804_ops = {
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.error_handler = nv_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.data_xfer = ata_data_xfer,
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.irq_handler = nv_ck804_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -452,7 +449,6 @@ static const struct ata_port_operations nv_adma_ops = {
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.error_handler = nv_adma_error_handler,
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.post_internal_cmd = nv_adma_post_internal_cmd,
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.data_xfer = ata_data_xfer,
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.irq_handler = nv_adma_interrupt,
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.irq_clear = nv_adma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -477,6 +473,7 @@ static struct ata_port_info nv_port_info[] = {
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_generic_ops,
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.irq_handler = nv_generic_interrupt,
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},
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/* nforce2/3 */
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{
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@ -487,6 +484,7 @@ static struct ata_port_info nv_port_info[] = {
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_nf2_ops,
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.irq_handler = nv_nf2_interrupt,
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},
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/* ck804 */
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{
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@ -497,6 +495,7 @@ static struct ata_port_info nv_port_info[] = {
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_ck804_ops,
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.irq_handler = nv_ck804_interrupt,
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},
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/* ADMA */
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{
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@ -508,6 +507,7 @@ static struct ata_port_info nv_port_info[] = {
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.mwdma_mask = NV_MWDMA_MASK,
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.udma_mask = NV_UDMA_MASK,
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.port_ops = &nv_adma_ops,
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.irq_handler = nv_adma_interrupt,
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},
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};
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@ -1079,14 +1079,14 @@ static int nv_adma_port_resume(struct ata_port *ap)
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}
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#endif
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static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port)
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static void nv_adma_setup_port(struct ata_port *ap)
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{
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void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR];
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struct ata_ioports *ioport = &probe_ent->port[port];
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void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
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struct ata_ioports *ioport = &ap->ioaddr;
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VPRINTK("ENTER\n");
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mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE;
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mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
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ioport->cmd_addr = mmio;
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ioport->data_addr = mmio + (ATA_REG_DATA * 4);
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@ -1103,9 +1103,9 @@ static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int por
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ioport->ctl_addr = mmio + 0x20;
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}
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static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
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static int nv_adma_host_init(struct ata_host *host)
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{
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struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
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struct pci_dev *pdev = to_pci_dev(host->dev);
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unsigned int i;
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u32 tmp32;
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@ -1120,8 +1120,8 @@ static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
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pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
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for (i = 0; i < probe_ent->n_ports; i++)
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nv_adma_setup_port(probe_ent, i);
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for (i = 0; i < host->n_ports; i++)
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nv_adma_setup_port(host->ports[i]);
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return 0;
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}
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@ -1480,14 +1480,13 @@ static void nv_adma_error_handler(struct ata_port *ap)
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static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version = 0;
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struct ata_port_info *ppi[2];
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struct ata_probe_ent *probe_ent;
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const struct ata_port_info *ppi[2];
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struct ata_host *host;
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struct nv_host_priv *hpriv;
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int rc;
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u32 bar;
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void __iomem *base;
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unsigned long type = ent->driver_data;
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int mask_set = 0;
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// Make sure this is a SATA controller by counting the number of bars
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// (NVIDIA SATA controllers will always have six bars). Otherwise,
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@ -1503,50 +1502,38 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pcim_pin_device(pdev);
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return rc;
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}
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if(type >= CK804 && adma_enabled) {
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/* determine type and allocate host */
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if (type >= CK804 && adma_enabled) {
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dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
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type = ADMA;
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if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
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!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
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mask_set = 1;
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}
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if(!mask_set) {
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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}
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rc = -ENOMEM;
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ppi[0] = ppi[1] = &nv_port_info[type];
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rc = ata_pci_prepare_native_host(pdev, ppi, 2, &host);
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if (rc)
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return rc;
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hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
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if (!hpriv)
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return -ENOMEM;
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ppi[0] = ppi[1] = &nv_port_info[type];
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent)
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return -ENOMEM;
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if (!pcim_iomap(pdev, NV_MMIO_BAR, 0))
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return -EIO;
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probe_ent->iomap = pcim_iomap_table(pdev);
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probe_ent->private_data = hpriv;
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hpriv->type = type;
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host->private_data = hpriv;
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base = probe_ent->iomap[NV_MMIO_BAR];
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probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
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probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
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/* set 64bit dma masks, may fail */
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if (type == ADMA) {
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if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
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pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
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}
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/* request and iomap NV_MMIO_BAR */
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rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
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if (rc)
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return rc;
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/* configure SCR access */
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base = host->iomap[NV_MMIO_BAR];
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host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
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host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
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/* enable SATA space for CK804 */
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if (type >= CK804) {
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@ -1557,20 +1544,16 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
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}
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pci_set_master(pdev);
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/* init ADMA */
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if (type == ADMA) {
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rc = nv_adma_host_init(probe_ent);
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rc = nv_adma_host_init(host);
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if (rc)
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return rc;
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}
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rc = ata_device_add(probe_ent);
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if (rc != NV_PORTS)
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return -ENODEV;
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devm_kfree(&pdev->dev, probe_ent);
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return 0;
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pci_set_master(pdev);
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return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
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IRQF_SHARED, ppi[0]->sht);
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}
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static void nv_remove_one (struct pci_dev *pdev)
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@ -121,7 +121,6 @@ static const struct ata_port_operations sis_ops = {
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -131,7 +130,6 @@ static const struct ata_port_operations sis_ops = {
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};
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static struct ata_port_info sis_port_info = {
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.sht = &sis_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x7,
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@ -256,12 +254,13 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct ata_probe_ent *probe_ent = NULL;
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int rc;
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struct ata_port_info pi = sis_port_info;
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const struct ata_port_info *ppi[2] = { &pi, &pi };
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struct ata_host *host;
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u32 genctl, val;
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struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
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u8 pmr;
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u8 port2_start = 0x20;
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int rc;
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if (!printed_version++)
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dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
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@ -270,19 +269,6 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pcim_pin_device(pdev);
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return rc;
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}
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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/* check and see if the SCRs are in IO space or PCI cfg space */
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pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
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if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
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@ -349,30 +335,26 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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break;
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}
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent)
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return -ENOMEM;
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rc = ata_pci_prepare_native_host(pdev, ppi, 2, &host);
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if (rc)
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return rc;
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if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
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if (!(pi.flags & SIS_FLAG_CFGSCR)) {
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void __iomem *mmio;
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mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0);
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if (!mmio)
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return -ENOMEM;
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rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
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if (rc)
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return rc;
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mmio = host->iomap[SIS_SCR_PCI_BAR];
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probe_ent->port[0].scr_addr = mmio;
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probe_ent->port[1].scr_addr = mmio + port2_start;
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host->ports[0]->ioaddr.scr_addr = mmio;
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host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
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}
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pci_set_master(pdev);
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pci_intx(pdev, 1);
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if (!ata_device_add(probe_ent))
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return -EIO;
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devm_kfree(&pdev->dev, probe_ent);
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return 0;
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return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
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&sis_sht);
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}
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static int __init sis_init(void)
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@ -115,7 +115,6 @@ static const struct ata_port_operations uli_ops = {
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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@ -127,7 +126,6 @@ static const struct ata_port_operations uli_ops = {
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};
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static struct ata_port_info uli_port_info = {
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.sht = &uli_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_IGN_SIMPLEX,
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.pio_mask = 0x1f, /* pio0-4 */
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@ -185,12 +183,13 @@ static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct ata_probe_ent *probe_ent;
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struct ata_port_info *ppi[2];
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int rc;
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const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
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unsigned int board_idx = (unsigned int) ent->driver_data;
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struct ata_host *host;
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struct uli_priv *hpriv;
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void __iomem * const *iomap;
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struct ata_ioports *ioaddr;
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int n_ports, rc;
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if (!printed_version++)
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dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
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@ -199,54 +198,42 @@ static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pcim_pin_device(pdev);
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return rc;
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}
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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n_ports = 2;
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if (board_idx == uli_5287)
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n_ports = 4;
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rc = ata_pci_prepare_native_host(pdev, ppi, n_ports, &host);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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ppi[0] = ppi[1] = &uli_port_info;
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent)
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return -ENOMEM;
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hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
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if (!hpriv)
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return -ENOMEM;
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host->private_data = hpriv;
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probe_ent->private_data = hpriv;
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iomap = pcim_iomap_table(pdev);
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iomap = host->iomap;
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switch (board_idx) {
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case uli_5287:
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hpriv->scr_cfg_addr[0] = ULI5287_BASE;
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hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
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probe_ent->n_ports = 4;
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probe_ent->port[2].cmd_addr = iomap[0] + 8;
|
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probe_ent->port[2].altstatus_addr =
|
||||
probe_ent->port[2].ctl_addr = (void __iomem *)
|
||||
ioaddr = &host->ports[2]->ioaddr;
|
||||
ioaddr->cmd_addr = iomap[0] + 8;
|
||||
ioaddr->altstatus_addr =
|
||||
ioaddr->ctl_addr = (void __iomem *)
|
||||
((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
|
||||
probe_ent->port[2].bmdma_addr = iomap[4] + 16;
|
||||
ioaddr->bmdma_addr = iomap[4] + 16;
|
||||
hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
|
||||
ata_std_ports(ioaddr);
|
||||
|
||||
probe_ent->port[3].cmd_addr = iomap[2] + 8;
|
||||
probe_ent->port[3].altstatus_addr =
|
||||
probe_ent->port[3].ctl_addr = (void __iomem *)
|
||||
ioaddr = &host->ports[3]->ioaddr;
|
||||
ioaddr->cmd_addr = iomap[2] + 8;
|
||||
ioaddr->altstatus_addr =
|
||||
ioaddr->ctl_addr = (void __iomem *)
|
||||
((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
|
||||
probe_ent->port[3].bmdma_addr = iomap[4] + 24;
|
||||
ioaddr->bmdma_addr = iomap[4] + 24;
|
||||
hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
|
||||
|
||||
ata_std_ports(&probe_ent->port[2]);
|
||||
ata_std_ports(&probe_ent->port[3]);
|
||||
ata_std_ports(ioaddr);
|
||||
break;
|
||||
|
||||
case uli_5289:
|
||||
|
|
@ -266,12 +253,8 @@ static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
|
||||
pci_set_master(pdev);
|
||||
pci_intx(pdev, 1);
|
||||
|
||||
if (!ata_device_add(probe_ent))
|
||||
return -ENODEV;
|
||||
|
||||
devm_kfree(&pdev->dev, probe_ent);
|
||||
return 0;
|
||||
return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
|
||||
&uli_sht);
|
||||
}
|
||||
|
||||
static int __init uli_init(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue