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ARM: SoC driver updates for v4.10 

Driver updates for ARM SoCs, including a couple of newly added drivers:
 
 - A new driver for the power management controller on TI Keystone
 - Support for the prerelease "SCPI" firmware protocol that ended up
   being shipped by Amlogic in their GXBB SoC.
 - A soc_device can now be matched using a glob from inside the
   kernel, when another driver wants to know the specific chip
   it is running on and cannot find out from DT, firmware or hardware.
 - Renesas SoCs now support identification through the soc_device
   interface, both in user space and kernel.
 - Renesas r8a7743 and r8a7745 gain support for their system controller
 - A new checking module for the ARM "PSCI" (not to be confused
   with "SCPI" mentioned above) firmware interface.
 - A new driver for the Tegra GMI memory interface
 - Support for the Tegra firmware interfaces with their
   power management controllers
 
 As usual, the updates for the reset controller framework are merged
 here, as they tend to touch multiple SoCs as well, including a new
 driver for the Oxford (now Broadcom) OX820 chip and the Tegra
 bpmp interface.
 
 The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and
 Rockchips SoCs see some further updates.
 
 Conflicts:
 - ARCH_RENESAS now selects SOC_BUS, but no longer needs GPIOLIB
 - drivers/soc/renesas/Makefile: multiple files got added, keep
   all in logical sorting
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs, including a couple of newly added
  drivers:

   - A new driver for the power management controller on TI Keystone

   - Support for the prerelease "SCPI" firmware protocol that ended up
     being shipped by Amlogic in their GXBB SoC.

   - A soc_device can now be matched using a glob from inside the
     kernel, when another driver wants to know the specific chip it is
     running on and cannot find out from DT, firmware or hardware.

   - Renesas SoCs now support identification through the soc_device
     interface, both in user space and kernel.

   - Renesas r8a7743 and r8a7745 gain support for their system
     controller

   - A new checking module for the ARM "PSCI" (not to be confused with
     "SCPI" mentioned above) firmware interface.

   - A new driver for the Tegra GMI memory interface

   - Support for the Tegra firmware interfaces with their power
     management controllers

  As usual, the updates for the reset controller framework are merged
  here, as they tend to touch multiple SoCs as well, including a new
  driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp
  interface.

  The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and
  Rockchips SoCs see some further updates"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits)
  misc: sram: remove useless #ifdef
  drivers: psci: Allow PSCI node to be disabled
  drivers: psci: PSCI checker module
  soc: renesas: Identify SoC and register with the SoC bus
  firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails
  firmware: qcom: scm: Remove core, iface and bus clocks dependency
  dt-bindings: firmware: scm: Add MSM8996 DT bindings
  memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name()
  bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name()
  ARM: shmobile: Document DT bindings for Product Register
  soc: renesas: rcar-sysc: add R8A7745 support
  reset: Add Tegra BPMP reset driver
  dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
  dt-bindings: Add power domains to Tegra BPMP firmware
  firmware: tegra: Add BPMP support
  firmware: tegra: Add IVC library
  dt-bindings: firmware: Add bindings for Tegra BPMP
  mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
  mailbox: Add Tegra HSP driver
  firmware: arm_scpi: add support for pre-v1.0 SCPI compatible
  ...
This commit is contained in:
Linus Torvalds 2016-12-15 16:03:25 -08:00
parent 482c3e8835 2ada959322
commit 991688bfc6
86 changed files with 11443 additions and 737 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/devicetree/bindings/arm/amlogic,scpi.txt Normal file
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@ -0,0 +1,20 @@
System Control and Power Interface (SCPI) Message Protocol
(in addition to the standard binding in [0])
----------------------------------------------------------
Required properties
- compatible : should be "amlogic,meson-gxbb-scpi"
AMLOGIC SRAM and Shared Memory for SCPI
------------------------------------
Required properties:
- compatible : should be "amlogic,meson-gxbb-sram"
Each sub-node represents the reserved area for SCPI.
Required sub-node properties:
- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
memory on Amlogic GXBB SoC.
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt

25
Documentation/devicetree/bindings/arm/arm,scpi.txt
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@ -7,7 +7,10 @@ by Linux to initiate various system control and power operations.
Required properties:
- compatible : should be "arm,scpi"
- compatible : should be
* "arm,scpi" : For implementations complying to SCPI v1.0 or above
* "arm,scpi-pre-1.0" : For implementations complying to all
unversioned releases prior to SCPI v1.0
- mboxes: List of phandle and mailbox channel specifiers
All the channels reserved by remote SCP firmware for use by
SCPI message protocol should be specified in any order
@ -59,18 +62,14 @@ SRAM and Shared Memory for SCPI
A small area of SRAM is reserved for SCPI communication between application
processors and SCP.
Required properties:
- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
The rest of the properties should follow the generic mmio-sram description
found in ../../sram/sram.txt
The properties should follow the generic mmio-sram description found in [3]
Each sub-node represents the reserved area for SCPI.
Required sub-node properties:
- reg : The base offset and size of the reserved area with the SRAM
- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
shared memory on Juno platforms
- compatible : should be "arm,scp-shmem" for Non-secure SRAM based
shared memory
Sensor bindings for the sensors based on SCPI Message Protocol
--------------------------------------------------------------
@ -81,11 +80,9 @@ Required properties:
- #thermal-sensor-cells: should be set to 1. This property follows the
thermal device tree bindings[2].
Valid cell values are raw identifiers (Sensor
ID) as used by the firmware. Refer to
platform documentation for your
implementation for the IDs to use. For Juno
R0 and Juno R1 refer to [3].
Valid cell values are raw identifiers (Sensor ID)
as used by the firmware. Refer to platform details
for your implementation for the IDs to use.
Power domain bindings for the power domains based on SCPI Message Protocol
------------------------------------------------------------
@ -112,7 +109,7 @@ Required properties:
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/thermal/thermal.txt
[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
[3] Documentation/devicetree/bindings/sram/sram.txt
[4] Documentation/devicetree/bindings/power/power_domain.txt
Example:

16
Documentation/devicetree/bindings/arm/atmel-at91.txt
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@ -225,3 +225,19 @@ required properties:
compatible = "atmel,sama5d3-sfr", "syscon";
reg = <0xf0038000 0x60>;
};
Security Module (SECUMOD)
The Security Module macrocell provides all necessary secure functions to avoid
voltage, temperature, frequency and mechanical attacks on the chip. It also
embeds secure memories that can be scrambled
required properties:
- compatible: Should be "atmel,<chip>-secumod", "syscon".
<chip> can be "sama5d2".
- reg: Should contain registers location and length
secumod@fc040000 {
compatible = "atmel,sama5d2-secumod", "syscon";
reg = <0xfc040000 0x100>;
};

26
Documentation/devicetree/bindings/arm/juno,scpi.txt Normal file
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@ -0,0 +1,26 @@
System Control and Power Interface (SCPI) Message Protocol
(in addition to the standard binding in [0])
Juno SRAM and Shared Memory for SCPI
------------------------------------
Required properties:
- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
Each sub-node represents the reserved area for SCPI.
Required sub-node properties:
- reg : The base offset and size of the reserved area with the SRAM
- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
shared memory on Juno platforms
Sensor bindings for the sensors based on SCPI Message Protocol
--------------------------------------------------------------
Required properties:
- compatible : should be "arm,scpi-sensors".
- #thermal-sensor-cells: should be set to 1.
For Juno R0 and Juno R1 refer to [1] for the
sensor identifiers
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html

81
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Texas Instruments System Control Interface (TI-SCI) Message Protocol
--------------------------------------------------------------------
Texas Instrument's processors including those belonging to Keystone generation
of processors have separate hardware entity which is now responsible for the
management of the System on Chip (SoC) system. These include various system
level functions as well.
An example of such an SoC is K2G, which contains the system control hardware
block called Power Management Micro Controller (PMMC). This hardware block is
initialized early into boot process and provides services to Operating Systems
on multiple processors including ones running Linux.
See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
TI-SCI controller Device Node:
=============================
The TI-SCI node describes the Texas Instrument's System Controller entity node.
This parent node may optionally have additional children nodes which describe
specific functionality such as clocks, power domain, reset or additional
functionality as may be required for the SoC. This hierarchy also describes the
relationship between the TI-SCI parent node to the child node.
Required properties:
-------------------
- compatible: should be "ti,k2g-sci"
- mbox-names:
"rx" - Mailbox corresponding to receive path
"tx" - Mailbox corresponding to transmit path
- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
property should contain a phandle to the mailbox controller device
node and an args specifier that will be the phandle to the intended
sub-mailbox child node to be used for communication.
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
about the generic mailbox controller and client driver bindings. Also see
Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical
controller that is used to communicate with this System controllers.
Optional Properties:
-------------------
- reg-names:
debug_messages - Map the Debug message region
- reg: register space corresponding to the debug_messages
- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
Example (K2G):
-------------
pmmc: pmmc {
compatible = "ti,k2g-sci";
mbox-names = "rx", "tx";
mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
<&msgmgr &msgmgr_proxy_pmmc_tx>;
reg-names = "debug_messages";
reg = <0x02921800 0x800>;
};
TI-SCI Client Device Node:
=========================
Client nodes are maintained as children of the relevant TI-SCI device node.
Example (K2G):
-------------
pmmc: pmmc {
compatible = "ti,k2g-sci";
...
my_clk_node: clk_node {
...
...
};
my_pd_node: pd_node {
...
...
};
};

18
Documentation/devicetree/bindings/arm/shmobile.txt
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@ -85,3 +85,21 @@ Boards:
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"
Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
product and revision information. If present, a device node for this register
should be added.
Required properties:
- compatible: Must be "renesas,prr".
- reg: Base address and length of the register block.
Examples
--------
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};

132
Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt Normal file
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@ -0,0 +1,132 @@
Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
The Generic Memory Interface bus enables memory transfers between internal and
external memory. Can be used to attach various high speed devices such as
synchronous/asynchronous NOR, FPGA, UARTS and more.
The actual devices are instantiated from the child nodes of a GMI node.
Required properties:
- compatible : Should contain one of the following:
For Tegra20 must contain "nvidia,tegra20-gmi".
For Tegra30 must contain "nvidia,tegra30-gmi".
- reg: Should contain GMI controller registers location and length.
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries: "gmi"
- resets : Must contain an entry for each entry in reset-names.
- reset-names : Must include the following entries: "gmi"
- #address-cells: The number of cells used to represent physical base
addresses in the GMI address space. Should be 2.
- #size-cells: The number of cells used to represent the size of an address
range in the GMI address space. Should be 1.
- ranges: Must be set up to reflect the memory layout with three integer values
for each chip-select line in use (only one entry is supported, see below
comments):
<cs-number> <offset> <physical address of mapping> <size>
Note that the GMI controller does not have any internal chip-select address
decoding, because of that chip-selects either need to be managed via software
or by employing external chip-select decoding logic.
If external chip-select logic is used to support multiple devices it is assumed
that the devices use the same timing and so are probably the same type. It also
assumes that they can fit in the 256MB address range. In this case only one
child device is supported which represents the active chip-select line, see
examples for more insight.
The chip-select number is decoded from the child nodes second address cell of
'ranges' property, if 'ranges' property is not present or empty chip-select will
then be decoded from the first cell of the 'reg' property.
Optional child cs node properties:
- nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
- nvidia,snor-mux-mode: Enable address/data MUX mode.
- nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
If omitted it will be asserted with data.
- nvidia,snor-rdy-active-high: RDY signal is active high
- nvidia,snor-adv-active-high: ADV signal is active high
- nvidia,snor-oe-active-high: WE/OE signal is active high
- nvidia,snor-cs-active-high: CS signal is active high
Note that there is some special handling for the timing values.
From Tegra TRM:
Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
- nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
bus. Valid values are 0-15, default is 1
- nvidia,snor-hold-width: Number of cycles CE stays asserted after the
de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
(in case of MASTER Request). Valid values are 0-15, default is 1
- nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
Valid values are 0-15, default is 1.
- nvidia,snor-ce-width: Number of cycles before CE is asserted.
Valid values are 0-15, default is 4
- nvidia,snor-we-width: Number of cycles during which WE stays asserted.
Valid values are 0-15, default is 1
- nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
Valid values are 0-255, default is 1
- nvidia,snor-wait-width: Number of cycles before READY is asserted.
Valid values are 0-255, default is 3
Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
gmi@70090000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
clocks = <&tegra_car TEGRA20_CLK_NOR>;
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
status = "okay";
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 4 0 0x40100>;
nvidia,snor-mux-mode;
nvidia,snor-adv-active-high;
can@0 {
reg = <0 0x100>;
...
};
can@40000 {
reg = <0x40000 0x100>;
...
};
};
};
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
gmi@70090000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
clocks = <&tegra_car TEGRA20_CLK_NOR>;
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
status = "okay";
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;
nvidia,snor-adv-active-high;
...
};
};

20
Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt Normal file
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@ -0,0 +1,20 @@
* Device tree bindings for Texas Instruments da8xx master peripheral
priority driver
DA8XX SoCs feature a set of registers allowing to change the priority of all
peripherals classified as masters.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
Required properties:
- compatible: "ti,da850-mstpri" - for da850 based boards
- reg: offset and length of the mstpri registers
Example for da850-lcdk is shown below.
mstpri {
compatible = "ti,da850-mstpri";
reg = <0x14110 0x0c>;
};

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@ -0,0 +1,108 @@
NVIDIA Tegra Boot and Power Management Processor (BPMP)
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
defines the resources that would be used by the BPMP firmware driver,
which can create the interprocessor communication (IPC) between the CPU
and BPMP.
Required properties:
- name : Should be bpmp
- compatible
Array of strings
One of:
- "nvidia,tegra186-bpmp"
- mboxes : The phandle of mailbox controller and the mailbox specifier.
- shmem : List of the phandle of the TX and RX shared memory area that
the IPC between CPU and BPMP is based on.
- #clock-cells : Should be 1.
- #power-domain-cells : Should be 1.
- #reset-cells : Should be 1.
This node is a mailbox consumer. See the following files for details of
the mailbox subsystem, and the specifiers implemented by the relevant
provider(s):
- .../mailbox/mailbox.txt
- .../mailbox/nvidia,tegra186-hsp.txt
This node is a clock, power domain, and reset provider. See the following
files for general documentation of those features, and the specifiers
implemented by this node:
- .../clock/clock-bindings.txt
- <dt-bindings/clock/tegra186-clock.h>
- ../power/power_domain.txt
- <dt-bindings/power/tegra186-powergate.h>
- .../reset/reset.txt
- <dt-bindings/reset/tegra186-reset.h>
The BPMP implements some services which must be represented by separate nodes.
For example, it can provide access to certain I2C controllers, and the I2C
bindings represent each I2C controller as a device tree node. Such nodes should
be nested directly inside the main BPMP node.
Software can determine whether a child node of the BPMP node represents a device
by checking for a compatible property. Any node with a compatible property
represents a device that can be instantiated. Nodes without a compatible
property may be used to provide configuration information regarding the BPMP
itself, although no such configuration nodes are currently defined by this
binding.
The BPMP firmware defines no single global name-/numbering-space for such
services. Put another way, the numbering scheme for I2C buses is distinct from
the numbering scheme for any other service the BPMP may provide (e.g. a future
hypothetical SPI bus service). As such, child device nodes will have no reg
property, and the BPMP node will have no #address-cells or #size-cells property.
The shared memory bindings for BPMP
-----------------------------------
The shared memory area for the IPC TX and RX between CPU and BPMP are
predefined and work on top of sysram, which is an SRAM inside the chip.
See ".../sram/sram.txt" for the bindings.
Example:
hsp_top0: hsp@03c00000 {
...
#mbox-cells = <2>;
};
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
cpu_bpmp_tx: shmem@4e000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4e000 0x0 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: shmem@4f000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4f000 0x0 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
};
bpmp {
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
i2c {
compatible = "...";
...
};
};

2
Documentation/devicetree/bindings/firmware/qcom,scm.txt
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@ -10,8 +10,10 @@ Required properties:
* "qcom,scm-apq8064" for APQ8064 platforms
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
* No clock required for "qcom,scm-msm8996"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface

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@ -0,0 +1,52 @@
NVIDIA Tegra Hardware Synchronization Primitives (HSP)
The HSP modules are used for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives for
interprocessor communication. So the interprocessor communication (IPC)
protocols can use hardware synchronization primitives, when operating between
two processors not in an SMP relationship.
The features that HSP supported are shared mailboxes, shared semaphores,
arbitrated semaphores and doorbells.
Required properties:
- name : Should be hsp
- compatible
Array of strings.
one of:
- "nvidia,tegra186-hsp"
- reg : Offset and length of the register set for the device.
- interrupt-names
Array of strings.
Contains a list of names for the interrupts described by the interrupt
property. May contain the following entries, in any order:
- "doorbell"
Users of this binding MUST look up entries in the interrupt property
by name, using this interrupt-names property to do so.
- interrupts
Array of interrupt specifiers.
Must contain one entry per entry in the interrupt-names property,
in a matching order.
- #mbox-cells : Should be 2.
The mbox specifier of the "mboxes" property in the client node should
contain two data. The first one should be the HSP type and the second
one should be the ID that the client is going to use. Those information
can be found in the following file.
- <dt-bindings/mailbox/tegra186-hsp.h>.
Example:
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x0 0x03c00000 0x0 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
#mbox-cells = <2>;
};
client {
...
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
};

20
Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt Normal file
View File

@ -0,0 +1,20 @@
* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features
a set of registers which allow to tweak the controller's behavior.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
Required properties:
- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards
- reg: a tuple containing the base address of the memory
controller and the size of the memory area to map
Example for da850 shown below.
ddrctl {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
};

8
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
View File

@ -1,12 +1,14 @@
DT bindings for the Renesas R-Car System Controller
DT bindings for the Renesas R-Car (RZ/G) System Controller
== System Controller Node ==
The R-Car System Controller provides power management for the CPU cores and
various coprocessors.
The R-Car (RZ/G) System Controller provides power management for the CPU cores
and various coprocessors.
Required properties:
- compatible: Must contain exactly one of the following:
- "renesas,r8a7743-sysc" (RZ/G1M)
- "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)

44
Documentation/devicetree/bindings/reset/oxnas,reset.txt
View File

@ -5,45 +5,19 @@ Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "oxsemi,ox810se-reset"
- compatible: For OX810SE, should be "oxsemi,ox810se-reset"
For OX820, should be "oxsemi,ox820-reset"
- #reset-cells: 1, see below
Parent node should have the following properties :
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
- compatible: For OX810SE, should be :
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
For OX820, should be :
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
For OX810SE, the indices are :
- 0 : ARM
- 1 : COPRO
- 2 : Reserved
- 3 : Reserved
- 4 : USBHS
- 5 : USBHSPHY
- 6 : MAC
- 7 : PCI
- 8 : DMA
- 9 : DPE
- 10 : DDR
- 11 : SATA
- 12 : SATA_LINK
- 13 : SATA_PHY
- 14 : Reserved
- 15 : NAND
- 16 : GPIO
- 17 : UART1
- 18 : UART2
- 19 : MISC
- 20 : I2S
- 21 : AHB_MON
- 22 : UART3
- 23 : UART4
- 24 : SGDMA
- 25 : Reserved
- 26 : Reserved
- 27 : Reserved
- 28 : Reserved
- 29 : Reserved
- 30 : Reserved
- 31 : BUS
Reset indices are in dt-bindings include files :
- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
- For OX820: include/dt-bindings/reset/oxsemi,ox820.h
example:

2
Documentation/devicetree/bindings/sram/sram.txt
View File

@ -4,7 +4,7 @@ Simple IO memory regions to be managed by the genalloc API.
Required properties:
- compatible : mmio-sram
- compatible : mmio-sram or atmel,sama5d2-securam
- reg : SRAM iomem address range

11
MAINTAINERS
View File

@ -1627,6 +1627,7 @@ F: arch/arm/mach-qcom/
F: arch/arm64/boot/dts/qcom/*
F: drivers/i2c/busses/i2c-qup.c
F: drivers/clk/qcom/
F: drivers/pinctrl/qcom/
F: drivers/soc/qcom/
F: drivers/spi/spi-qup.c
F: drivers/tty/serial/msm_serial.h
@ -12088,6 +12089,16 @@ S: Maintained
F: arch/xtensa/
F: drivers/irqchip/irq-xtensa-*
Texas Instruments' System Control Interface (TISCI) Protocol Driver
M: Nishanth Menon <nm@ti.com>
M: Tero Kristo <t-kristo@ti.com>
M: Santosh Shilimkar <ssantosh@kernel.org>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
F: drivers/firmware/ti_sci*
F: include/linux/soc/ti/ti_sci_protocol.h
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
L: linux-media@vger.kernel.org

1
arch/arm/mach-shmobile/Kconfig
View File

@ -41,6 +41,7 @@ menuconfig ARCH_RENESAS
select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
select SOC_BUS
select ZONE_DMA if ARM_LPAE
if ARCH_RENESAS

2
arch/arm/mach-sti/Kconfig
View File

@ -28,7 +28,6 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targeted at set-top-box
@ -38,7 +37,6 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targeted at set-top-box

1
arch/arm64/Kconfig.platforms
View File

@ -144,6 +144,7 @@ config ARCH_RENESAS
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select SOC_BUS
help
This enables support for the ARMv8 based Renesas SoCs.

16
drivers/bus/Kconfig
View File

@ -150,6 +150,13 @@ config TEGRA_ACONNECT
Driver for the Tegra ACONNECT bus which is used to interface with
the devices inside the Audio Processing Engine (APE) for Tegra210.
config TEGRA_GMI
tristate "Tegra Generic Memory Interface bus driver"
depends on ARCH_TEGRA
help
Driver for the Tegra Generic Memory Interface bus which can be used
to attach devices such as NOR, UART, FPGA and more.
config UNIPHIER_SYSTEM_BUS
tristate "UniPhier System Bus driver"
depends on ARCH_UNIPHIER && OF
@ -167,4 +174,13 @@ config VEXPRESS_CONFIG
help
Platform configuration infrastructure for the ARM Ltd.
Versatile Express.
config DA8XX_MSTPRI
bool "TI da8xx master peripheral priority driver"
depends on ARCH_DAVINCI_DA8XX
help
Driver for Texas Instruments da8xx master peripheral priority
configuration. Allows to adjust the priorities of all master
peripherals.
endmenu

3
drivers/bus/Makefile
View File

@ -19,5 +19,8 @@ obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
obj-$(CONFIG_DA8XX_MSTPRI) += da8xx-mstpri.o

267
drivers/bus/da8xx-mstpri.c Normal file
View File

@ -0,0 +1,267 @@
/*
* TI da8xx master peripheral priority driver
*
* Copyright (C) 2016 BayLibre SAS
*
* Author:
* Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/regmap.h>
/*
* REVISIT: Linux doesn't have a good framework for the kind of performance
* knobs this driver controls. We can't use device tree properties as it deals
* with hardware configuration rather than description. We also don't want to
* commit to maintaining some random sysfs attributes.
*
* For now we just hardcode the register values for the boards that need
* some changes (as is the case for the LCD controller on da850-lcdk - the
* first board we support here). When linux gets an appropriate framework,
* we'll easily convert the driver to it.
*/
#define DA8XX_MSTPRI0_OFFSET 0
#define DA8XX_MSTPRI1_OFFSET 4
#define DA8XX_MSTPRI2_OFFSET 8
enum {
DA8XX_MSTPRI_ARM_I = 0,
DA8XX_MSTPRI_ARM_D,
DA8XX_MSTPRI_UPP,
DA8XX_MSTPRI_SATA,
DA8XX_MSTPRI_PRU0,
DA8XX_MSTPRI_PRU1,
DA8XX_MSTPRI_EDMA30TC0,
DA8XX_MSTPRI_EDMA30TC1,
DA8XX_MSTPRI_EDMA31TC0,
DA8XX_MSTPRI_VPIF_DMA_0,
DA8XX_MSTPRI_VPIF_DMA_1,
DA8XX_MSTPRI_EMAC,
DA8XX_MSTPRI_USB0CFG,
DA8XX_MSTPRI_USB0CDMA,
DA8XX_MSTPRI_UHPI,
DA8XX_MSTPRI_USB1,
DA8XX_MSTPRI_LCDC,
};
struct da8xx_mstpri_descr {
int reg;
int shift;
int mask;
};
static const struct da8xx_mstpri_descr da8xx_mstpri_priority_list[] = {
[DA8XX_MSTPRI_ARM_I] = {
.reg = DA8XX_MSTPRI0_OFFSET,
.shift = 0,
.mask = 0x0000000f,
},
[DA8XX_MSTPRI_ARM_D] = {
.reg = DA8XX_MSTPRI0_OFFSET,
.shift = 4,
.mask = 0x000000f0,
},
[DA8XX_MSTPRI_UPP] = {
.reg = DA8XX_MSTPRI0_OFFSET,
.shift = 16,
.mask = 0x000f0000,
},
[DA8XX_MSTPRI_SATA] = {
.reg = DA8XX_MSTPRI0_OFFSET,
.shift = 20,
.mask = 0x00f00000,
},
[DA8XX_MSTPRI_PRU0] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 0,
.mask = 0x0000000f,
},
[DA8XX_MSTPRI_PRU1] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 4,
.mask = 0x000000f0,
},
[DA8XX_MSTPRI_EDMA30TC0] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 8,
.mask = 0x00000f00,
},
[DA8XX_MSTPRI_EDMA30TC1] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 12,
.mask = 0x0000f000,
},
[DA8XX_MSTPRI_EDMA31TC0] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 16,
.mask = 0x000f0000,
},
[DA8XX_MSTPRI_VPIF_DMA_0] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 24,
.mask = 0x0f000000,
},
[DA8XX_MSTPRI_VPIF_DMA_1] = {
.reg = DA8XX_MSTPRI1_OFFSET,
.shift = 28,
.mask = 0xf0000000,
},
[DA8XX_MSTPRI_EMAC] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 0,
.mask = 0x0000000f,
},
[DA8XX_MSTPRI_USB0CFG] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 8,
.mask = 0x00000f00,
},
[DA8XX_MSTPRI_USB0CDMA] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 12,
.mask = 0x0000f000,
},
[DA8XX_MSTPRI_UHPI] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 20,
.mask = 0x00f00000,
},
[DA8XX_MSTPRI_USB1] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 24,
.mask = 0x0f000000,
},
[DA8XX_MSTPRI_LCDC] = {
.reg = DA8XX_MSTPRI2_OFFSET,
.shift = 28,
.mask = 0xf0000000,
},
};
struct da8xx_mstpri_priority {
int which;
u32 val;
};
struct da8xx_mstpri_board_priorities {
const char *board;
const struct da8xx_mstpri_priority *priorities;
size_t numprio;
};
/*
* Default memory settings of da850 do not meet the throughput/latency
* requirements of tilcdc. This results in the image displayed being
* incorrect and the following warning being displayed by the LCDC
* drm driver:
*
* tilcdc da8xx_lcdc.0: tilcdc_crtc_irq(0x00000020): FIFO underfow
*/
static const struct da8xx_mstpri_priority da850_lcdk_priorities[] = {
{
.which = DA8XX_MSTPRI_LCDC,
.val = 0,
},
{
.which = DA8XX_MSTPRI_EDMA30TC1,
.val = 0,
},
{
.which = DA8XX_MSTPRI_EDMA30TC0,
.val = 1,
},
};
static const struct da8xx_mstpri_board_priorities da8xx_mstpri_board_confs[] = {
{
.board = "ti,da850-lcdk",
.priorities = da850_lcdk_priorities,
.numprio = ARRAY_SIZE(da850_lcdk_priorities),
},
};
static const struct da8xx_mstpri_board_priorities *
da8xx_mstpri_get_board_prio(void)
{
const struct da8xx_mstpri_board_priorities *board_prio;
int i;
for (i = 0; i < ARRAY_SIZE(da8xx_mstpri_board_confs); i++) {
board_prio = &da8xx_mstpri_board_confs[i];
if (of_machine_is_compatible(board_prio->board))
return board_prio;
}
return NULL;
}
static int da8xx_mstpri_probe(struct platform_device *pdev)
{
const struct da8xx_mstpri_board_priorities *prio_list;
const struct da8xx_mstpri_descr *prio_descr;
const struct da8xx_mstpri_priority *prio;
struct device *dev = &pdev->dev;
struct resource *res;
void __iomem *mstpri;
u32 reg;
int i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mstpri = devm_ioremap_resource(dev, res);
if (IS_ERR(mstpri)) {
dev_err(dev, "unable to map MSTPRI registers\n");
return PTR_ERR(mstpri);
}
prio_list = da8xx_mstpri_get_board_prio();
if (!prio_list) {
dev_err(dev, "no master priorities defined for this board\n");
return -EINVAL;
}
for (i = 0; i < prio_list->numprio; i++) {
prio = &prio_list->priorities[i];
prio_descr = &da8xx_mstpri_priority_list[prio->which];
if (prio_descr->reg + sizeof(u32) > resource_size(res)) {
dev_warn(dev, "register offset out of range\n");
continue;
}
reg = readl(mstpri + prio_descr->reg);
reg &= ~prio_descr->mask;
reg |= prio->val << prio_descr->shift;
writel(reg, mstpri + prio_descr->reg);
}
return 0;
}
static const struct of_device_id da8xx_mstpri_of_match[] = {
{ .compatible = "ti,da850-mstpri", },
{ },
};
static struct platform_driver da8xx_mstpri_driver = {
.probe = da8xx_mstpri_probe,
.driver = {
.name = "da8xx-mstpri",
.of_match_table = da8xx_mstpri_of_match,
},
};
module_platform_driver(da8xx_mstpri_driver);
MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
MODULE_DESCRIPTION("TI da8xx master peripheral priority driver");
MODULE_LICENSE("GPL v2");

284
drivers/bus/tegra-gmi.c Normal file
View File

@ -0,0 +1,284 @@
/*
* Driver for NVIDIA Generic Memory Interface
*
* Copyright (C) 2016 Host Mobility AB. All rights reserved.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#define TEGRA_GMI_CONFIG 0x00
#define TEGRA_GMI_CONFIG_GO BIT(31)
#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
#define TEGRA_GMI_MUX_MODE BIT(28)
#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
#define TEGRA_GMI_TIMING0 0x10
#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
#define TEGRA_GMI_TIMING1 0x14
#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
#define TEGRA_GMI_MAX_CHIP_SELECT 8
struct tegra_gmi {
struct device *dev;
void __iomem *base;
struct clk *clk;
struct reset_control *rst;
u32 snor_config;
u32 snor_timing0;
u32 snor_timing1;
};
static int tegra_gmi_enable(struct tegra_gmi *gmi)
{
int err;
err = clk_prepare_enable(gmi->clk);
if (err < 0) {
dev_err(gmi->dev, "failed to enable clock: %d\n", err);
return err;
}
reset_control_assert(gmi->rst);
usleep_range(2000, 4000);
reset_control_deassert(gmi->rst);
writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
return 0;
}
static void tegra_gmi_disable(struct tegra_gmi *gmi)
{
u32 config;
/* stop GMI operation */
config = readl(gmi->base + TEGRA_GMI_CONFIG);
config &= ~TEGRA_GMI_CONFIG_GO;
writel(config, gmi->base + TEGRA_GMI_CONFIG);
reset_control_assert(gmi->rst);
clk_disable_unprepare(gmi->clk);
}
static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
{
struct device_node *child;
u32 property, ranges[4];
int err;
child = of_get_next_available_child(gmi->dev->of_node, NULL);
if (!child) {
dev_err(gmi->dev, "no child nodes found\n");
return -ENODEV;
}
/*
* We currently only support one child device due to lack of
* chip-select address decoding. Which means that we only have one
* chip-select line from the GMI controller.
*/
if (of_get_child_count(gmi->dev->of_node) > 1)
dev_warn(gmi->dev, "only one child device is supported.");
if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
gmi->snor_config |= TEGRA_GMI_MUX_MODE;
if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
/* Decode the CS# */
err = of_property_read_u32_array(child, "ranges", ranges, 4);
if (err < 0) {
/* Invalid binding */
if (err == -EOVERFLOW) {
dev_err(gmi->dev,
"failed to decode CS: invalid ranges length\n");
goto error_cs;
}
/*
* If we reach here it means that the child node has an empty
* ranges or it does not exist at all. Attempt to decode the
* CS# from the reg property instead.
*/
err = of_property_read_u32(child, "reg", &property);
if (err < 0) {
dev_err(gmi->dev,
"failed to decode CS: no reg property found\n");
goto error_cs;
}
} else {
property = ranges[1];
}
/* Valid chip selects are CS0-CS7 */
if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
dev_err(gmi->dev, "invalid chip select: %d", property);
err = -EINVAL;
goto error_cs;
}
gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
/* The default values that are provided below are reset values */
if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
else
gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
else
gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
else
gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
else
gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
else
gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
else
gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
else
gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
error_cs:
of_node_put(child);
return err;
}
static int tegra_gmi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra_gmi *gmi;
struct resource *res;
int err;
gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
if (!gmi)
return -ENOMEM;
gmi->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
gmi->base = devm_ioremap_resource(dev, res);
if (IS_ERR(gmi->base))
return PTR_ERR(gmi->base);
gmi->clk = devm_clk_get(dev, "gmi");
if (IS_ERR(gmi->clk)) {
dev_err(dev, "can not get clock\n");
return PTR_ERR(gmi->clk);
}
gmi->rst = devm_reset_control_get(dev, "gmi");
if (IS_ERR(gmi->rst)) {
dev_err(dev, "can not get reset\n");
return PTR_ERR(gmi->rst);
}
err = tegra_gmi_parse_dt(gmi);
if (err)
return err;
err = tegra_gmi_enable(gmi);
if (err < 0)
return err;
err = of_platform_default_populate(dev->of_node, NULL, dev);
if (err < 0) {
dev_err(dev, "fail to create devices.\n");
tegra_gmi_disable(gmi);
return err;
}
platform_set_drvdata(pdev, gmi);
return 0;
}
static int tegra_gmi_remove(struct platform_device *pdev)
{
struct tegra_gmi *gmi = platform_get_drvdata(pdev);
of_platform_depopulate(gmi->dev);
tegra_gmi_disable(gmi);
return 0;
}
static const struct of_device_id tegra_gmi_id_table[] = {
{ .compatible = "nvidia,tegra20-gmi", },
{ .compatible = "nvidia,tegra30-gmi", },
{ }
};
MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
static struct platform_driver tegra_gmi_driver = {
.probe = tegra_gmi_probe,
.remove = tegra_gmi_remove,
.driver = {
.name = "tegra-gmi",
.of_match_table = tegra_gmi_id_table,
},
};
module_platform_driver(tegra_gmi_driver);
MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
MODULE_LICENSE("GPL v2");

27
drivers/firmware/Kconfig
View File

@ -8,6 +8,17 @@ menu "Firmware Drivers"
config ARM_PSCI_FW
bool
config ARM_PSCI_CHECKER
bool "ARM PSCI checker"
depends on ARM_PSCI_FW && HOTPLUG_CPU && !TORTURE_TEST
help
Run the PSCI checker during startup. This checks that hotplug and
suspend operations work correctly when using PSCI.
The torture tests may interfere with the PSCI checker by turning CPUs
on and off through hotplug, so for now torture tests and PSCI checker
are mutually exclusive.
config ARM_SCPI_PROTOCOL
tristate "ARM System Control and Power Interface (SCPI) Message Protocol"
depends on MAILBOX
@ -203,6 +214,21 @@ config QCOM_SCM_64
def_bool y
depends on QCOM_SCM && ARM64
config TI_SCI_PROTOCOL
tristate "TI System Control Interface (TISCI) Message Protocol"
depends on TI_MESSAGE_MANAGER
help
TI System Control Interface (TISCI) Message Protocol is used to manage
compute systems such as ARM, DSP etc with the system controller in
complex System on Chip(SoC) such as those found on certain keystone
generation SoC from TI.
System controller provides various facilities including power
management function support.
This protocol library is used by client drivers to use the features
provided by the system controller.
config HAVE_ARM_SMCCC
bool
@ -210,5 +236,6 @@ source "drivers/firmware/broadcom/Kconfig"
source "drivers/firmware/google/Kconfig"
source "drivers/firmware/efi/Kconfig"
source "drivers/firmware/meson/Kconfig"
source "drivers/firmware/tegra/Kconfig"
endmenu

3
drivers/firmware/Makefile
View File

@ -2,6 +2,7 @@
# Makefile for the linux kernel.
#
obj-$(CONFIG_ARM_PSCI_FW) += psci.o
obj-$(CONFIG_ARM_PSCI_CHECKER) += psci_checker.o
obj-$(CONFIG_ARM_SCPI_PROTOCOL) += arm_scpi.o
obj-$(CONFIG_ARM_SCPI_POWER_DOMAIN) += scpi_pm_domain.o
obj-$(CONFIG_DMI) += dmi_scan.o
@ -20,9 +21,11 @@ obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-y += broadcom/
obj-y += meson/
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
obj-$(CONFIG_UEFI_CPER) += efi/
obj-y += tegra/

276
drivers/firmware/arm_scpi.c
View File

@ -50,20 +50,27 @@
#define CMD_TOKEN_ID_MASK 0xff
#define CMD_DATA_SIZE_SHIFT 16
#define CMD_DATA_SIZE_MASK 0x1ff
#define CMD_LEGACY_DATA_SIZE_SHIFT 20
#define CMD_LEGACY_DATA_SIZE_MASK 0x1ff
#define PACK_SCPI_CMD(cmd_id, tx_sz) \
((((cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
(((tx_sz) & CMD_DATA_SIZE_MASK) << CMD_DATA_SIZE_SHIFT))
#define ADD_SCPI_TOKEN(cmd, token) \
((cmd) |= (((token) & CMD_TOKEN_ID_MASK) << CMD_TOKEN_ID_SHIFT))
#define PACK_LEGACY_SCPI_CMD(cmd_id, tx_sz) \
((((cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
(((tx_sz) & CMD_LEGACY_DATA_SIZE_MASK) << CMD_LEGACY_DATA_SIZE_SHIFT))
#define CMD_SIZE(cmd) (((cmd) >> CMD_DATA_SIZE_SHIFT) & CMD_DATA_SIZE_MASK)
#define CMD_LEGACY_SIZE(cmd) (((cmd) >> CMD_LEGACY_DATA_SIZE_SHIFT) & \
CMD_LEGACY_DATA_SIZE_MASK)
#define CMD_UNIQ_MASK (CMD_TOKEN_ID_MASK << CMD_TOKEN_ID_SHIFT | CMD_ID_MASK)
#define CMD_XTRACT_UNIQ(cmd) ((cmd) & CMD_UNIQ_MASK)
#define SCPI_SLOT 0
#define MAX_DVFS_DOMAINS 8
#define MAX_DVFS_OPPS 8
#define MAX_DVFS_OPPS 16
#define DVFS_LATENCY(hdr) (le32_to_cpu(hdr) >> 16)
#define DVFS_OPP_COUNT(hdr) ((le32_to_cpu(hdr) >> 8) & 0xff)
@ -99,6 +106,7 @@ enum scpi_error_codes {
SCPI_ERR_MAX
};
/* SCPI Standard commands */
enum scpi_std_cmd {
SCPI_CMD_INVALID = 0x00,
SCPI_CMD_SCPI_READY = 0x01,
@ -132,6 +140,108 @@ enum scpi_std_cmd {
SCPI_CMD_COUNT
};
/* SCPI Legacy Commands */
enum legacy_scpi_std_cmd {
LEGACY_SCPI_CMD_INVALID = 0x00,
LEGACY_SCPI_CMD_SCPI_READY = 0x01,
LEGACY_SCPI_CMD_SCPI_CAPABILITIES = 0x02,
LEGACY_SCPI_CMD_EVENT = 0x03,
LEGACY_SCPI_CMD_SET_CSS_PWR_STATE = 0x04,
LEGACY_SCPI_CMD_GET_CSS_PWR_STATE = 0x05,
LEGACY_SCPI_CMD_CFG_PWR_STATE_STAT = 0x06,
LEGACY_SCPI_CMD_GET_PWR_STATE_STAT = 0x07,
LEGACY_SCPI_CMD_SYS_PWR_STATE = 0x08,
LEGACY_SCPI_CMD_L2_READY = 0x09,
LEGACY_SCPI_CMD_SET_AP_TIMER = 0x0a,
LEGACY_SCPI_CMD_CANCEL_AP_TIME = 0x0b,
LEGACY_SCPI_CMD_DVFS_CAPABILITIES = 0x0c,
LEGACY_SCPI_CMD_GET_DVFS_INFO = 0x0d,
LEGACY_SCPI_CMD_SET_DVFS = 0x0e,
LEGACY_SCPI_CMD_GET_DVFS = 0x0f,
LEGACY_SCPI_CMD_GET_DVFS_STAT = 0x10,
LEGACY_SCPI_CMD_SET_RTC = 0x11,
LEGACY_SCPI_CMD_GET_RTC = 0x12,
LEGACY_SCPI_CMD_CLOCK_CAPABILITIES = 0x13,
LEGACY_SCPI_CMD_SET_CLOCK_INDEX = 0x14,
LEGACY_SCPI_CMD_SET_CLOCK_VALUE = 0x15,
LEGACY_SCPI_CMD_GET_CLOCK_VALUE = 0x16,
LEGACY_SCPI_CMD_PSU_CAPABILITIES = 0x17,
LEGACY_SCPI_CMD_SET_PSU = 0x18,
LEGACY_SCPI_CMD_GET_PSU = 0x19,
LEGACY_SCPI_CMD_SENSOR_CAPABILITIES = 0x1a,
LEGACY_SCPI_CMD_SENSOR_INFO = 0x1b,
LEGACY_SCPI_CMD_SENSOR_VALUE = 0x1c,
LEGACY_SCPI_CMD_SENSOR_CFG_PERIODIC = 0x1d,
LEGACY_SCPI_CMD_SENSOR_CFG_BOUNDS = 0x1e,
LEGACY_SCPI_CMD_SENSOR_ASYNC_VALUE = 0x1f,
LEGACY_SCPI_CMD_COUNT
};
/* List all commands that are required to go through the high priority link */
static int legacy_hpriority_cmds[] = {
LEGACY_SCPI_CMD_GET_CSS_PWR_STATE,
LEGACY_SCPI_CMD_CFG_PWR_STATE_STAT,
LEGACY_SCPI_CMD_GET_PWR_STATE_STAT,
LEGACY_SCPI_CMD_SET_DVFS,
LEGACY_SCPI_CMD_GET_DVFS,
LEGACY_SCPI_CMD_SET_RTC,
LEGACY_SCPI_CMD_GET_RTC,
LEGACY_SCPI_CMD_SET_CLOCK_INDEX,
LEGACY_SCPI_CMD_SET_CLOCK_VALUE,
LEGACY_SCPI_CMD_GET_CLOCK_VALUE,
LEGACY_SCPI_CMD_SET_PSU,
LEGACY_SCPI_CMD_GET_PSU,
LEGACY_SCPI_CMD_SENSOR_CFG_PERIODIC,
LEGACY_SCPI_CMD_SENSOR_CFG_BOUNDS,
};
/* List all commands used by this driver, used as indexes */
enum scpi_drv_cmds {
CMD_SCPI_CAPABILITIES = 0,
CMD_GET_CLOCK_INFO,
CMD_GET_CLOCK_VALUE,
CMD_SET_CLOCK_VALUE,
CMD_GET_DVFS,
CMD_SET_DVFS,
CMD_GET_DVFS_INFO,
CMD_SENSOR_CAPABILITIES,
CMD_SENSOR_INFO,
CMD_SENSOR_VALUE,
CMD_SET_DEVICE_PWR_STATE,
CMD_GET_DEVICE_PWR_STATE,
CMD_MAX_COUNT,
};
static int scpi_std_commands[CMD_MAX_COUNT] = {
SCPI_CMD_SCPI_CAPABILITIES,
SCPI_CMD_GET_CLOCK_INFO,
SCPI_CMD_GET_CLOCK_VALUE,
SCPI_CMD_SET_CLOCK_VALUE,
SCPI_CMD_GET_DVFS,
SCPI_CMD_SET_DVFS,
SCPI_CMD_GET_DVFS_INFO,
SCPI_CMD_SENSOR_CAPABILITIES,
SCPI_CMD_SENSOR_INFO,
SCPI_CMD_SENSOR_VALUE,
SCPI_CMD_SET_DEVICE_PWR_STATE,
SCPI_CMD_GET_DEVICE_PWR_STATE,
};
static int scpi_legacy_commands[CMD_MAX_COUNT] = {
LEGACY_SCPI_CMD_SCPI_CAPABILITIES,
-1, /* GET_CLOCK_INFO */
LEGACY_SCPI_CMD_GET_CLOCK_VALUE,
LEGACY_SCPI_CMD_SET_CLOCK_VALUE,
LEGACY_SCPI_CMD_GET_DVFS,
LEGACY_SCPI_CMD_SET_DVFS,
LEGACY_SCPI_CMD_GET_DVFS_INFO,
LEGACY_SCPI_CMD_SENSOR_CAPABILITIES,
LEGACY_SCPI_CMD_SENSOR_INFO,
LEGACY_SCPI_CMD_SENSOR_VALUE,
-1, /* SET_DEVICE_PWR_STATE */
-1, /* GET_DEVICE_PWR_STATE */
};
struct scpi_xfer {
u32 slot; /* has to be first element */
u32 cmd;
@ -160,7 +270,10 @@ struct scpi_chan {
struct scpi_drvinfo {
u32 protocol_version;
u32 firmware_version;
bool is_legacy;
int num_chans;
int *commands;
DECLARE_BITMAP(cmd_priority, LEGACY_SCPI_CMD_COUNT);
atomic_t next_chan;
struct scpi_ops *scpi_ops;
struct scpi_chan *channels;
@ -177,6 +290,11 @@ struct scpi_shared_mem {
u8 payload[0];
} __packed;
struct legacy_scpi_shared_mem {
__le32 status;
u8 payload[0];
} __packed;
struct scp_capabilities {
__le32 protocol_version;
__le32 event_version;
@ -202,6 +320,12 @@ struct clk_set_value {
__le32 rate;
} __packed;
struct legacy_clk_set_value {
__le32 rate;
__le16 id;
__le16 reserved;
} __packed;
struct dvfs_info {
__le32 header;
struct {
@ -273,19 +397,43 @@ static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd)
return;
}
list_for_each_entry(t, &ch->rx_pending, node)
if (CMD_XTRACT_UNIQ(t->cmd) == CMD_XTRACT_UNIQ(cmd)) {
list_del(&t->node);
match = t;
break;
}
/* Command type is not replied by the SCP Firmware in legacy Mode
* We should consider that command is the head of pending RX commands
* if the list is not empty. In TX only mode, the list would be empty.
*/
if (scpi_info->is_legacy) {
match = list_first_entry(&ch->rx_pending, struct scpi_xfer,
node);
list_del(&match->node);
} else {
list_for_each_entry(t, &ch->rx_pending, node)
if (CMD_XTRACT_UNIQ(t->cmd) == CMD_XTRACT_UNIQ(cmd)) {
list_del(&t->node);
match = t;
break;
}
}
/* check if wait_for_completion is in progress or timed-out */
if (match && !completion_done(&match->done)) {
struct scpi_shared_mem *mem = ch->rx_payload;
unsigned int len = min(match->rx_len, CMD_SIZE(cmd));
unsigned int len;
if (scpi_info->is_legacy) {
struct legacy_scpi_shared_mem *mem = ch->rx_payload;
/* RX Length is not replied by the legacy Firmware */
len = match->rx_len;
match->status = le32_to_cpu(mem->status);
memcpy_fromio(match->rx_buf, mem->payload, len);
} else {
struct scpi_shared_mem *mem = ch->rx_payload;
len = min(match->rx_len, CMD_SIZE(cmd));
match->status = le32_to_cpu(mem->status);
memcpy_fromio(match->rx_buf, mem->payload, len);
}
match->status = le32_to_cpu(mem->status);
memcpy_fromio(match->rx_buf, mem->payload, len);
if (match->rx_len > len)
memset(match->rx_buf + len, 0, match->rx_len - len);
complete(&match->done);
@ -297,7 +445,10 @@ static void scpi_handle_remote_msg(struct mbox_client *c, void *msg)
{
struct scpi_chan *ch = container_of(c, struct scpi_chan, cl);
struct scpi_shared_mem *mem = ch->rx_payload;
u32 cmd = le32_to_cpu(mem->command);
u32 cmd = 0;
if (!scpi_info->is_legacy)
cmd = le32_to_cpu(mem->command);
scpi_process_cmd(ch, cmd);
}
@ -309,8 +460,13 @@ static void scpi_tx_prepare(struct mbox_client *c, void *msg)
struct scpi_chan *ch = container_of(c, struct scpi_chan, cl);
struct scpi_shared_mem *mem = (struct scpi_shared_mem *)ch->tx_payload;
if (t->tx_buf)
memcpy_toio(mem->payload, t->tx_buf, t->tx_len);
if (t->tx_buf) {
if (scpi_info->is_legacy)
memcpy_toio(ch->tx_payload, t->tx_buf, t->tx_len);
else
memcpy_toio(mem->payload, t->tx_buf, t->tx_len);
}
if (t->rx_buf) {
if (!(++ch->token))
++ch->token;
@ -319,7 +475,9 @@ static void scpi_tx_prepare(struct mbox_client *c, void *msg)
list_add_tail(&t->node, &ch->rx_pending);
spin_unlock_irqrestore(&ch->rx_lock, flags);
}
mem->command = cpu_to_le32(t->cmd);
if (!scpi_info->is_legacy)
mem->command = cpu_to_le32(t->cmd);
}
static struct scpi_xfer *get_scpi_xfer(struct scpi_chan *ch)
@ -344,23 +502,38 @@ static void put_scpi_xfer(struct scpi_xfer *t, struct scpi_chan *ch)
mutex_unlock(&ch->xfers_lock);
}
static int scpi_send_message(u8 cmd, void *tx_buf, unsigned int tx_len,
static int scpi_send_message(u8 idx, void *tx_buf, unsigned int tx_len,
void *rx_buf, unsigned int rx_len)
{
int ret;
u8 chan;
u8 cmd;
struct scpi_xfer *msg;
struct scpi_chan *scpi_chan;
chan = atomic_inc_return(&scpi_info->next_chan) % scpi_info->num_chans;
if (scpi_info->commands[idx] < 0)
return -EOPNOTSUPP;
cmd = scpi_info->commands[idx];
if (scpi_info->is_legacy)
chan = test_bit(cmd, scpi_info->cmd_priority) ? 1 : 0;
else
chan = atomic_inc_return(&scpi_info->next_chan) %
scpi_info->num_chans;
scpi_chan = scpi_info->channels + chan;
msg = get_scpi_xfer(scpi_chan);
if (!msg)
return -ENOMEM;
msg->slot = BIT(SCPI_SLOT);
msg->cmd = PACK_SCPI_CMD(cmd, tx_len);
if (scpi_info->is_legacy) {
msg->cmd = PACK_LEGACY_SCPI_CMD(cmd, tx_len);
msg->slot = msg->cmd;
} else {
msg->slot = BIT(SCPI_SLOT);
msg->cmd = PACK_SCPI_CMD(cmd, tx_len);
}
msg->tx_buf = tx_buf;
msg->tx_len = tx_len;
msg->rx_buf = rx_buf;
@ -397,7 +570,7 @@ scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max)
struct clk_get_info clk;
__le16 le_clk_id = cpu_to_le16(clk_id);
ret = scpi_send_message(SCPI_CMD_GET_CLOCK_INFO, &le_clk_id,
ret = scpi_send_message(CMD_GET_CLOCK_INFO, &le_clk_id,
sizeof(le_clk_id), &clk, sizeof(clk));
if (!ret) {
*min = le32_to_cpu(clk.min_rate);
@ -412,8 +585,9 @@ static unsigned long scpi_clk_get_val(u16 clk_id)
struct clk_get_value clk;
__le16 le_clk_id = cpu_to_le16(clk_id);
ret = scpi_send_message(SCPI_CMD_GET_CLOCK_VALUE, &le_clk_id,
ret = scpi_send_message(CMD_GET_CLOCK_VALUE, &le_clk_id,
sizeof(le_clk_id), &clk, sizeof(clk));
return ret ? ret : le32_to_cpu(clk.rate);
}
@ -425,7 +599,19 @@ static int scpi_clk_set_val(u16 clk_id, unsigned long rate)
.rate = cpu_to_le32(rate)
};
return scpi_send_message(SCPI_CMD_SET_CLOCK_VALUE, &clk, sizeof(clk),
return scpi_send_message(CMD_SET_CLOCK_VALUE, &clk, sizeof(clk),
&stat, sizeof(stat));
}
static int legacy_scpi_clk_set_val(u16 clk_id, unsigned long rate)
{
int stat;
struct legacy_clk_set_value clk = {
.id = cpu_to_le16(clk_id),
.rate = cpu_to_le32(rate)
};
return scpi_send_message(CMD_SET_CLOCK_VALUE, &clk, sizeof(clk),
&stat, sizeof(stat));
}
@ -434,8 +620,9 @@ static int scpi_dvfs_get_idx(u8 domain)
int ret;
u8 dvfs_idx;
ret = scpi_send_message(SCPI_CMD_GET_DVFS, &domain, sizeof(domain),
ret = scpi_send_message(CMD_GET_DVFS, &domain, sizeof(domain),
&dvfs_idx, sizeof(dvfs_idx));
return ret ? ret : dvfs_idx;
}
@ -444,7 +631,7 @@ static int scpi_dvfs_set_idx(u8 domain, u8 index)
int stat;
struct dvfs_set dvfs = {domain, index};
return scpi_send_message(SCPI_CMD_SET_DVFS, &dvfs, sizeof(dvfs),
return scpi_send_message(CMD_SET_DVFS, &dvfs, sizeof(dvfs),
&stat, sizeof(stat));
}
@ -468,9 +655,8 @@ static struct scpi_dvfs_info *scpi_dvfs_get_info(u8 domain)
if (scpi_info->dvfs[domain]) /* data already populated */
return scpi_info->dvfs[domain];
ret = scpi_send_message(SCPI_CMD_GET_DVFS_INFO, &domain, sizeof(domain),
ret = scpi_send_message(CMD_GET_DVFS_INFO, &domain, sizeof(domain),
&buf, sizeof(buf));
if (ret)
return ERR_PTR(ret);
@ -503,7 +689,7 @@ static int scpi_sensor_get_capability(u16 *sensors)
struct sensor_capabilities cap_buf;
int ret;
ret = scpi_send_message(SCPI_CMD_SENSOR_CAPABILITIES, NULL, 0, &cap_buf,
ret = scpi_send_message(CMD_SENSOR_CAPABILITIES, NULL, 0, &cap_buf,
sizeof(cap_buf));
if (!ret)
*sensors = le16_to_cpu(cap_buf.sensors);
@ -517,7 +703,7 @@ static int scpi_sensor_get_info(u16 sensor_id, struct scpi_sensor_info *info)
struct _scpi_sensor_info _info;
int ret;
ret = scpi_send_message(SCPI_CMD_SENSOR_INFO, &id, sizeof(id),
ret = scpi_send_message(CMD_SENSOR_INFO, &id, sizeof(id),
&_info, sizeof(_info));
if (!ret) {
memcpy(info, &_info, sizeof(*info));
@ -533,7 +719,7 @@ static int scpi_sensor_get_value(u16 sensor, u64 *val)
struct sensor_value buf;
int ret;
ret = scpi_send_message(SCPI_CMD_SENSOR_VALUE, &id, sizeof(id),
ret = scpi_send_message(CMD_SENSOR_VALUE, &id, sizeof(id),
&buf, sizeof(buf));
if (!ret)
*val = (u64)le32_to_cpu(buf.hi_val) << 32 |
@ -548,7 +734,7 @@ static int scpi_device_get_power_state(u16 dev_id)
u8 pstate;
__le16 id = cpu_to_le16(dev_id);
ret = scpi_send_message(SCPI_CMD_GET_DEVICE_PWR_STATE, &id,
ret = scpi_send_message(CMD_GET_DEVICE_PWR_STATE, &id,
sizeof(id), &pstate, sizeof(pstate));
return ret ? ret : pstate;
}
@ -561,7 +747,7 @@ static int scpi_device_set_power_state(u16 dev_id, u8 pstate)
.pstate = pstate,
};
return scpi_send_message(SCPI_CMD_SET_DEVICE_PWR_STATE, &dev_set,
return scpi_send_message(CMD_SET_DEVICE_PWR_STATE, &dev_set,
sizeof(dev_set), &stat, sizeof(stat));
}
@ -591,12 +777,16 @@ static int scpi_init_versions(struct scpi_drvinfo *info)
int ret;
struct scp_capabilities caps;
ret = scpi_send_message(SCPI_CMD_SCPI_CAPABILITIES, NULL, 0,
ret = scpi_send_message(CMD_SCPI_CAPABILITIES, NULL, 0,
&caps, sizeof(caps));
if (!ret) {
info->protocol_version = le32_to_cpu(caps.protocol_version);
info->firmware_version = le32_to_cpu(caps.platform_version);
}
/* Ignore error if not implemented */
if (scpi_info->is_legacy && ret == -EOPNOTSUPP)
return 0;
return ret;
}
@ -681,6 +871,11 @@ static int scpi_alloc_xfer_list(struct device *dev, struct scpi_chan *ch)
return 0;
}
static const struct of_device_id legacy_scpi_of_match[] = {
{.compatible = "arm,scpi-pre-1.0"},
{},
};
static int scpi_probe(struct platform_device *pdev)
{
int count, idx, ret;
@ -693,6 +888,9 @@ static int scpi_probe(struct platform_device *pdev)
if (!scpi_info)
return -ENOMEM;
if (of_match_device(legacy_scpi_of_match, &pdev->dev))
scpi_info->is_legacy = true;
count = of_count_phandle_with_args(np, "mboxes", "#mbox-cells");
if (count < 0) {
dev_err(dev, "no mboxes property in '%s'\n", np->full_name);
@ -755,8 +953,21 @@ err:
scpi_info->channels = scpi_chan;
scpi_info->num_chans = count;
scpi_info->commands = scpi_std_commands;
platform_set_drvdata(pdev, scpi_info);
if (scpi_info->is_legacy) {
/* Replace with legacy variants */
scpi_ops.clk_set_val = legacy_scpi_clk_set_val;
scpi_info->commands = scpi_legacy_commands;
/* Fill priority bitmap */
for (idx = 0; idx < ARRAY_SIZE(legacy_hpriority_cmds); idx++)
set_bit(legacy_hpriority_cmds[idx],
scpi_info->cmd_priority);
}
ret = scpi_init_versions(scpi_info);
if (ret) {
dev_err(dev, "incorrect or no SCP firmware found\n");
@ -781,6 +992,7 @@ err:
static const struct of_device_id scpi_of_match[] = {
{.compatible = "arm,scpi"},
{.compatible = "arm,scpi-pre-1.0"},
{},
};

2
drivers/firmware/psci.c
View File

@ -630,7 +630,7 @@ int __init psci_dt_init(void)
np = of_find_matching_node_and_match(NULL, psci_of_match, &matched_np);
if (!np)
if (!np || !of_device_is_available(np))
return -ENODEV;
init_fn = (psci_initcall_t)matched_np->data;

490
drivers/firmware/psci_checker.c Normal file
View File

@ -0,0 +1,490 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2016 ARM Limited
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/atomic.h>
#include <linux/completion.h>
#include <linux/cpu.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/preempt.h>
#include <linux/psci.h>
#include <linux/slab.h>
#include <linux/tick.h>
#include <linux/topology.h>
#include <asm/cpuidle.h>
#include <uapi/linux/psci.h>
#define NUM_SUSPEND_CYCLE (10)
static unsigned int nb_available_cpus;
static int tos_resident_cpu = -1;
static atomic_t nb_active_threads;
static struct completion suspend_threads_started =
COMPLETION_INITIALIZER(suspend_threads_started);
static struct completion suspend_threads_done =
COMPLETION_INITIALIZER(suspend_threads_done);
/*
* We assume that PSCI operations are used if they are available. This is not
* necessarily true on arm64, since the decision is based on the
* "enable-method" property of each CPU in the DT, but given that there is no
* arch-specific way to check this, we assume that the DT is sensible.
*/
static int psci_ops_check(void)
{
int migrate_type = -1;
int cpu;
if (!(psci_ops.cpu_off && psci_ops.cpu_on && psci_ops.cpu_suspend)) {
pr_warn("Missing PSCI operations, aborting tests\n");
return -EOPNOTSUPP;
}
if (psci_ops.migrate_info_type)
migrate_type = psci_ops.migrate_info_type();
if (migrate_type == PSCI_0_2_TOS_UP_MIGRATE ||
migrate_type == PSCI_0_2_TOS_UP_NO_MIGRATE) {
/* There is a UP Trusted OS, find on which core it resides. */
for_each_online_cpu(cpu)
if (psci_tos_resident_on(cpu)) {
tos_resident_cpu = cpu;
break;
}
if (tos_resident_cpu == -1)
pr_warn("UP Trusted OS resides on no online CPU\n");
}
return 0;
}
static int find_clusters(const struct cpumask *cpus,
const struct cpumask **clusters)
{
unsigned int nb = 0;
cpumask_var_t tmp;
if (!alloc_cpumask_var(&tmp, GFP_KERNEL))
return -ENOMEM;
cpumask_copy(tmp, cpus);
while (!cpumask_empty(tmp)) {
const struct cpumask *cluster =
topology_core_cpumask(cpumask_any(tmp));
clusters[nb++] = cluster;
cpumask_andnot(tmp, tmp, cluster);
}
free_cpumask_var(tmp);
return nb;
}
/*
* offlined_cpus is a temporary array but passing it as an argument avoids
* multiple allocations.
*/
static unsigned int down_and_up_cpus(const struct cpumask *cpus,
struct cpumask *offlined_cpus)
{
int cpu;
int err = 0;
cpumask_clear(offlined_cpus);
/* Try to power down all CPUs in the mask. */
for_each_cpu(cpu, cpus) {
int ret = cpu_down(cpu);
/*
* cpu_down() checks the number of online CPUs before the TOS
* resident CPU.
*/
if (cpumask_weight(offlined_cpus) + 1 == nb_available_cpus) {
if (ret != -EBUSY) {
pr_err("Unexpected return code %d while trying "
"to power down last online CPU %d\n",
ret, cpu);
++err;
}
} else if (cpu == tos_resident_cpu) {
if (ret != -EPERM) {
pr_err("Unexpected return code %d while trying "
"to power down TOS resident CPU %d\n",
ret, cpu);
++err;
}
} else if (ret != 0) {
pr_err("Error occurred (%d) while trying "
"to power down CPU %d\n", ret, cpu);
++err;
}
if (ret == 0)
cpumask_set_cpu(cpu, offlined_cpus);
}
/* Try to power up all the CPUs that have been offlined. */
for_each_cpu(cpu, offlined_cpus) {
int ret = cpu_up(cpu);
if (ret != 0) {
pr_err("Error occurred (%d) while trying "
"to power up CPU %d\n", ret, cpu);
++err;
} else {
cpumask_clear_cpu(cpu, offlined_cpus);
}
}
/*
* Something went bad at some point and some CPUs could not be turned
* back on.
*/
WARN_ON(!cpumask_empty(offlined_cpus) ||
num_online_cpus() != nb_available_cpus);
return err;
}
static int hotplug_tests(void)
{
int err;
cpumask_var_t offlined_cpus;
int i, nb_cluster;
const struct cpumask **clusters;
char *page_buf;
err = -ENOMEM;
if (!alloc_cpumask_var(&offlined_cpus, GFP_KERNEL))
return err;
/* We may have up to nb_available_cpus clusters. */
clusters = kmalloc_array(nb_available_cpus, sizeof(*clusters),
GFP_KERNEL);
if (!clusters)
goto out_free_cpus;
page_buf = (char *)__get_free_page(GFP_KERNEL);
if (!page_buf)
goto out_free_clusters;
err = 0;
nb_cluster = find_clusters(cpu_online_mask, clusters);
/*
* Of course the last CPU cannot be powered down and cpu_down() should
* refuse doing that.
*/
pr_info("Trying to turn off and on again all CPUs\n");
err += down_and_up_cpus(cpu_online_mask, offlined_cpus);
/*
* Take down CPUs by cluster this time. When the last CPU is turned
* off, the cluster itself should shut down.
*/
for (i = 0; i < nb_cluster; ++i) {
int cluster_id =
topology_physical_package_id(cpumask_any(clusters[i]));
ssize_t len = cpumap_print_to_pagebuf(true, page_buf,
clusters[i]);
/* Remove trailing newline. */
page_buf[len - 1] = '\0';
pr_info("Trying to turn off and on again cluster %d "
"(CPUs %s)\n", cluster_id, page_buf);
err += down_and_up_cpus(clusters[i], offlined_cpus);
}
free_page((unsigned long)page_buf);
out_free_clusters:
kfree(clusters);
out_free_cpus:
free_cpumask_var(offlined_cpus);
return err;
}
static void dummy_callback(unsigned long ignored) {}
static int suspend_cpu(int index, bool broadcast)
{
int ret;
arch_cpu_idle_enter();
if (broadcast) {
/*
* The local timer will be shut down, we need to enter tick
* broadcast.
*/
ret = tick_broadcast_enter();
if (ret) {
/*
* In the absence of hardware broadcast mechanism,
* this CPU might be used to broadcast wakeups, which
* may be why entering tick broadcast has failed.
* There is little the kernel can do to work around
* that, so enter WFI instead (idle state 0).
*/
cpu_do_idle();
ret = 0;
goto out_arch_exit;
}
}
/*
* Replicate the common ARM cpuidle enter function
* (arm_enter_idle_state).
*/
ret = CPU_PM_CPU_IDLE_ENTER(arm_cpuidle_suspend, index);
if (broadcast)
tick_broadcast_exit();
out_arch_exit:
arch_cpu_idle_exit();
return ret;
}
static int suspend_test_thread(void *arg)
{
int cpu = (long)arg;
int i, nb_suspend = 0, nb_shallow_sleep = 0, nb_err = 0;
struct sched_param sched_priority = { .sched_priority = MAX_RT_PRIO-1 };
struct cpuidle_device *dev;
struct cpuidle_driver *drv;
/* No need for an actual callback, we just want to wake up the CPU. */
struct timer_list wakeup_timer =
TIMER_INITIALIZER(dummy_callback, 0, 0);
/* Wait for the main thread to give the start signal. */
wait_for_completion(&suspend_threads_started);
/* Set maximum priority to preempt all other threads on this CPU. */
if (sched_setscheduler_nocheck(current, SCHED_FIFO, &sched_priority))
pr_warn("Failed to set suspend thread scheduler on CPU %d\n",
cpu);
dev = this_cpu_read(cpuidle_devices);
drv = cpuidle_get_cpu_driver(dev);
pr_info("CPU %d entering suspend cycles, states 1 through %d\n",
cpu, drv->state_count - 1);
for (i = 0; i < NUM_SUSPEND_CYCLE; ++i) {
int index;
/*
* Test all possible states, except 0 (which is usually WFI and
* doesn't use PSCI).
*/
for (index = 1; index < drv->state_count; ++index) {
struct cpuidle_state *state = &drv->states[index];
bool broadcast = state->flags & CPUIDLE_FLAG_TIMER_STOP;
int ret;
/*
* Set the timer to wake this CPU up in some time (which
* should be largely sufficient for entering suspend).
* If the local tick is disabled when entering suspend,
* suspend_cpu() takes care of switching to a broadcast
* tick, so the timer will still wake us up.
*/
mod_timer(&wakeup_timer, jiffies +
usecs_to_jiffies(state->target_residency));
/* IRQs must be disabled during suspend operations. */
local_irq_disable();
ret = suspend_cpu(index, broadcast);
/*
* We have woken up. Re-enable IRQs to handle any
* pending interrupt, do not wait until the end of the
* loop.
*/
local_irq_enable();
if (ret == index) {
++nb_suspend;
} else if (ret >= 0) {
/* We did not enter the expected state. */
++nb_shallow_sleep;
} else {
pr_err("Failed to suspend CPU %d: error %d "
"(requested state %d, cycle %d)\n",
cpu, ret, index, i);
++nb_err;
}
}
}
/*
* Disable the timer to make sure that the timer will not trigger
* later.
*/
del_timer(&wakeup_timer);
if (atomic_dec_return_relaxed(&nb_active_threads) == 0)
complete(&suspend_threads_done);
/* Give up on RT scheduling and wait for termination. */
sched_priority.sched_priority = 0;
if (sched_setscheduler_nocheck(current, SCHED_NORMAL, &sched_priority))
pr_warn("Failed to set suspend thread scheduler on CPU %d\n",
cpu);
for (;;) {
/* Needs to be set first to avoid missing a wakeup. */
set_current_state(TASK_INTERRUPTIBLE);
if (kthread_should_stop()) {
__set_current_state(TASK_RUNNING);
break;
}
schedule();
}
pr_info("CPU %d suspend test results: success %d, shallow states %d, errors %d\n",
cpu, nb_suspend, nb_shallow_sleep, nb_err);
return nb_err;
}
static int suspend_tests(void)
{
int i, cpu, err = 0;
struct task_struct **threads;
int nb_threads = 0;
threads = kmalloc_array(nb_available_cpus, sizeof(*threads),
GFP_KERNEL);
if (!threads)
return -ENOMEM;
/*
* Stop cpuidle to prevent the idle tasks from entering a deep sleep
* mode, as it might interfere with the suspend threads on other CPUs.
* This does not prevent the suspend threads from using cpuidle (only
* the idle tasks check this status). Take the idle lock so that
* the cpuidle driver and device look-up can be carried out safely.
*/
cpuidle_pause_and_lock();
for_each_online_cpu(cpu) {
struct task_struct *thread;
/* Check that cpuidle is available on that CPU. */
struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
if (!dev || !drv) {
pr_warn("cpuidle not available on CPU %d, ignoring\n",
cpu);
continue;
}
thread = kthread_create_on_cpu(suspend_test_thread,
(void *)(long)cpu, cpu,
"psci_suspend_test");
if (IS_ERR(thread))
pr_err("Failed to create kthread on CPU %d\n", cpu);
else
threads[nb_threads++] = thread;
}
if (nb_threads < 1) {
err = -ENODEV;
goto out;
}
atomic_set(&nb_active_threads, nb_threads);
/*
* Wake up the suspend threads. To avoid the main thread being preempted
* before all the threads have been unparked, the suspend threads will
* wait for the completion of suspend_threads_started.
*/
for (i = 0; i < nb_threads; ++i)
wake_up_process(threads[i]);
complete_all(&suspend_threads_started);
wait_for_completion(&suspend_threads_done);
/* Stop and destroy all threads, get return status. */
for (i = 0; i < nb_threads; ++i)
err += kthread_stop(threads[i]);
out:
cpuidle_resume_and_unlock();
kfree(threads);
return err;
}
static int __init psci_checker(void)
{
int ret;
/*
* Since we're in an initcall, we assume that all the CPUs that all
* CPUs that can be onlined have been onlined.
*
* The tests assume that hotplug is enabled but nobody else is using it,
* otherwise the results will be unpredictable. However, since there
* is no userspace yet in initcalls, that should be fine, as long as
* no torture test is running at the same time (see Kconfig).
*/
nb_available_cpus = num_online_cpus();
/* Check PSCI operations are set up and working. */
ret = psci_ops_check();
if (ret)
return ret;
pr_info("PSCI checker started using %u CPUs\n", nb_available_cpus);
pr_info("Starting hotplug tests\n");
ret = hotplug_tests();
if (ret == 0)
pr_info("Hotplug tests passed OK\n");
else if (ret > 0)
pr_err("%d error(s) encountered in hotplug tests\n", ret);
else {
pr_err("Out of memory\n");
return ret;
}
pr_info("Starting suspend tests (%d cycles per state)\n",
NUM_SUSPEND_CYCLE);
ret = suspend_tests();
if (ret == 0)
pr_info("Suspend tests passed OK\n");
else if (ret > 0)
pr_err("%d error(s) encountered in suspend tests\n", ret);
else {
switch (ret) {
case -ENOMEM:
pr_err("Out of memory\n");
break;
case -ENODEV:
pr_warn("Could not start suspend tests on any CPU\n");
break;
}
}
pr_info("PSCI checker completed\n");
return ret < 0 ? ret : 0;
}
late_initcall(psci_checker);

53
drivers/firmware/qcom_scm.c
View File

@ -28,6 +28,10 @@
#include "qcom_scm.h"
#define SCM_HAS_CORE_CLK BIT(0)
#define SCM_HAS_IFACE_CLK BIT(1)
#define SCM_HAS_BUS_CLK BIT(2)
struct qcom_scm {
struct device *dev;
struct clk *core_clk;
@ -323,32 +327,40 @@ EXPORT_SYMBOL(qcom_scm_is_available);
static int qcom_scm_probe(struct platform_device *pdev)
{
struct qcom_scm *scm;
unsigned long clks;
int ret;
scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
if (!scm)
return -ENOMEM;
scm->core_clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(scm->core_clk)) {
if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
clks = (unsigned long)of_device_get_match_data(&pdev->dev);
if (clks & SCM_HAS_CORE_CLK) {
scm->core_clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(scm->core_clk)) {
if (PTR_ERR(scm->core_clk) != -EPROBE_DEFER)
dev_err(&pdev->dev,
"failed to acquire core clk\n");
return PTR_ERR(scm->core_clk);
scm->core_clk = NULL;
}
}
if (of_device_is_compatible(pdev->dev.of_node, "qcom,scm")) {
if (clks & SCM_HAS_IFACE_CLK) {
scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
if (IS_ERR(scm->iface_clk)) {
if (PTR_ERR(scm->iface_clk) != -EPROBE_DEFER)
dev_err(&pdev->dev, "failed to acquire iface clk\n");
dev_err(&pdev->dev,
"failed to acquire iface clk\n");
return PTR_ERR(scm->iface_clk);
}
}
if (clks & SCM_HAS_BUS_CLK) {
scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(scm->bus_clk)) {
if (PTR_ERR(scm->bus_clk) != -EPROBE_DEFER)
dev_err(&pdev->dev, "failed to acquire bus clk\n");
dev_err(&pdev->dev,
"failed to acquire bus clk\n");
return PTR_ERR(scm->bus_clk);
}
}
@ -356,7 +368,9 @@ static int qcom_scm_probe(struct platform_device *pdev)
scm->reset.ops = &qcom_scm_pas_reset_ops;
scm->reset.nr_resets = 1;
scm->reset.of_node = pdev->dev.of_node;
reset_controller_register(&scm->reset);
ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
if (ret)
return ret;
/* vote for max clk rate for highest performance */
ret = clk_set_rate(scm->core_clk, INT_MAX);
@ -372,10 +386,23 @@ static int qcom_scm_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_scm_dt_match[] = {
{ .compatible = "qcom,scm-apq8064",},
{ .compatible = "qcom,scm-msm8660",},
{ .compatible = "qcom,scm-msm8960",},
{ .compatible = "qcom,scm",},
{ .compatible = "qcom,scm-apq8064",
.data = (void *) SCM_HAS_CORE_CLK,
},
{ .compatible = "qcom,scm-msm8660",
.data = (void *) SCM_HAS_CORE_CLK,
},
{ .compatible = "qcom,scm-msm8960",
.data = (void *) SCM_HAS_CORE_CLK,
},
{ .compatible = "qcom,scm-msm8996",
.data = NULL, /* no clocks */
},
{ .compatible = "qcom,scm",
.data = (void *)(SCM_HAS_CORE_CLK
| SCM_HAS_IFACE_CLK
| SCM_HAS_BUS_CLK),
},
{}
};

25
drivers/firmware/tegra/Kconfig Normal file
View File

@ -0,0 +1,25 @@
menu "Tegra firmware driver"
config TEGRA_IVC
bool "Tegra IVC protocol"
depends on ARCH_TEGRA
help
IVC (Inter-VM Communication) protocol is part of the IPC
(Inter Processor Communication) framework on Tegra. It maintains the
data and the different commuication channels in SysRAM or RAM and
keeps the content is synchronization between host CPU and remote
processors.
config TEGRA_BPMP
bool "Tegra BPMP driver"
depends on ARCH_TEGRA && TEGRA_HSP_MBOX && TEGRA_IVC
help
BPMP (Boot and Power Management Processor) is designed to off-loading
the PM functions which include clock/DVFS/thermal/power from the CPU.
It needs HSP as the HW synchronization and notification module and
IVC module as the message communication protocol.
This driver manages the IPC interface between host CPU and the
firmware running on BPMP.
endmenu

2
drivers/firmware/tegra/Makefile Normal file
View File

@ -0,0 +1,2 @@
obj-$(CONFIG_TEGRA_BPMP) += bpmp.o
obj-$(CONFIG_TEGRA_IVC) += ivc.o

868
drivers/firmware/tegra/bpmp.c Normal file
View File

@ -0,0 +1,868 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/clk/tegra.h>
#include <linux/genalloc.h>
#include <linux/mailbox_client.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/semaphore.h>
#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>
#include <soc/tegra/ivc.h>
#define MSG_ACK BIT(0)
#define MSG_RING BIT(1)
static inline struct tegra_bpmp *
mbox_client_to_bpmp(struct mbox_client *client)
{
return container_of(client, struct tegra_bpmp, mbox.client);
}
struct tegra_bpmp *tegra_bpmp_get(struct device *dev)
{
struct platform_device *pdev;
struct tegra_bpmp *bpmp;
struct device_node *np;
np = of_parse_phandle(dev->of_node, "nvidia,bpmp", 0);
if (!np)
return ERR_PTR(-ENOENT);
pdev = of_find_device_by_node(np);
if (!pdev) {
bpmp = ERR_PTR(-ENODEV);
goto put;
}
bpmp = platform_get_drvdata(pdev);
if (!bpmp) {
bpmp = ERR_PTR(-EPROBE_DEFER);
put_device(&pdev->dev);
goto put;
}
put:
of_node_put(np);
return bpmp;
}
EXPORT_SYMBOL_GPL(tegra_bpmp_get);
void tegra_bpmp_put(struct tegra_bpmp *bpmp)
{
if (bpmp)
put_device(bpmp->dev);
}
EXPORT_SYMBOL_GPL(tegra_bpmp_put);
static int tegra_bpmp_channel_get_index(struct tegra_bpmp_channel *channel)
{
return channel - channel->bpmp->channels;
}
static int
tegra_bpmp_channel_get_thread_index(struct tegra_bpmp_channel *channel)
{
struct tegra_bpmp *bpmp = channel->bpmp;
unsigned int offset, count;
int index;
offset = bpmp->soc->channels.thread.offset;
count = bpmp->soc->channels.thread.count;
index = tegra_bpmp_channel_get_index(channel);
if (index < 0)
return index;
if (index < offset || index >= offset + count)
return -EINVAL;
return index - offset;
}
static struct tegra_bpmp_channel *
tegra_bpmp_channel_get_thread(struct tegra_bpmp *bpmp, unsigned int index)
{
unsigned int offset = bpmp->soc->channels.thread.offset;
unsigned int count = bpmp->soc->channels.thread.count;
if (index >= count)
return NULL;
return &bpmp->channels[offset + index];
}
static struct tegra_bpmp_channel *
tegra_bpmp_channel_get_tx(struct tegra_bpmp *bpmp)
{
unsigned int offset = bpmp->soc->channels.cpu_tx.offset;
return &bpmp->channels[offset + smp_processor_id()];
}
static struct tegra_bpmp_channel *
tegra_bpmp_channel_get_rx(struct tegra_bpmp *bpmp)
{
unsigned int offset = bpmp->soc->channels.cpu_rx.offset;
return &bpmp->channels[offset];
}
static bool tegra_bpmp_message_valid(const struct tegra_bpmp_message *msg)
{
return (msg->tx.size <= MSG_DATA_MIN_SZ) &&
(msg->rx.size <= MSG_DATA_MIN_SZ) &&
(msg->tx.size == 0 || msg->tx.data) &&
(msg->rx.size == 0 || msg->rx.data);
}
static bool tegra_bpmp_master_acked(struct tegra_bpmp_channel *channel)
{
void *frame;
frame = tegra_ivc_read_get_next_frame(channel->ivc);
if (IS_ERR(frame)) {
channel->ib = NULL;
return false;
}
channel->ib = frame;
return true;
}
static int tegra_bpmp_wait_ack(struct tegra_bpmp_channel *channel)
{
unsigned long timeout = channel->bpmp->soc->channels.cpu_tx.timeout;
ktime_t end;
end = ktime_add_us(ktime_get(), timeout);
do {
if (tegra_bpmp_master_acked(channel))
return 0;
} while (ktime_before(ktime_get(), end));
return -ETIMEDOUT;
}
static bool tegra_bpmp_master_free(struct tegra_bpmp_channel *channel)
{
void *frame;
frame = tegra_ivc_write_get_next_frame(channel->ivc);
if (IS_ERR(frame)) {
channel->ob = NULL;
return false;
}
channel->ob = frame;
return true;
}
static int tegra_bpmp_wait_master_free(struct tegra_bpmp_channel *channel)
{
unsigned long timeout = channel->bpmp->soc->channels.cpu_tx.timeout;
ktime_t start, now;
start = ns_to_ktime(local_clock());
do {
if (tegra_bpmp_master_free(channel))
return 0;
now = ns_to_ktime(local_clock());
} while (ktime_us_delta(now, start) < timeout);
return -ETIMEDOUT;
}
static ssize_t __tegra_bpmp_channel_read(struct tegra_bpmp_channel *channel,
void *data, size_t size)
{
if (data && size > 0)
memcpy(data, channel->ib->data, size);
return tegra_ivc_read_advance(channel->ivc);
}
static ssize_t tegra_bpmp_channel_read(struct tegra_bpmp_channel *channel,
void *data, size_t size)
{
struct tegra_bpmp *bpmp = channel->bpmp;
unsigned long flags;
ssize_t err;
int index;
index = tegra_bpmp_channel_get_thread_index(channel);
if (index < 0)
return index;
spin_lock_irqsave(&bpmp->lock, flags);
err = __tegra_bpmp_channel_read(channel, data, size);
clear_bit(index, bpmp->threaded.allocated);
spin_unlock_irqrestore(&bpmp->lock, flags);
up(&bpmp->threaded.lock);
return err;
}
static ssize_t __tegra_bpmp_channel_write(struct tegra_bpmp_channel *channel,
unsigned int mrq, unsigned long flags,
const void *data, size_t size)
{
channel->ob->code = mrq;
channel->ob->flags = flags;
if (data && size > 0)
memcpy(channel->ob->data, data, size);
return tegra_ivc_write_advance(channel->ivc);
}
static struct tegra_bpmp_channel *
tegra_bpmp_write_threaded(struct tegra_bpmp *bpmp, unsigned int mrq,
const void *data, size_t size)
{
unsigned long timeout = bpmp->soc->channels.thread.timeout;
unsigned int count = bpmp->soc->channels.thread.count;
struct tegra_bpmp_channel *channel;
unsigned long flags;
unsigned int index;
int err;
err = down_timeout(&bpmp->threaded.lock, usecs_to_jiffies(timeout));
if (err < 0)
return ERR_PTR(err);
spin_lock_irqsave(&bpmp->lock, flags);
index = find_first_zero_bit(bpmp->threaded.allocated, count);
if (index == count) {
channel = ERR_PTR(-EBUSY);
goto unlock;
}
channel = tegra_bpmp_channel_get_thread(bpmp, index);
if (!channel) {
channel = ERR_PTR(-EINVAL);
goto unlock;
}
if (!tegra_bpmp_master_free(channel)) {
channel = ERR_PTR(-EBUSY);
goto unlock;
}
set_bit(index, bpmp->threaded.allocated);
err = __tegra_bpmp_channel_write(channel, mrq, MSG_ACK | MSG_RING,
data, size);
if (err < 0) {
clear_bit(index, bpmp->threaded.allocated);
goto unlock;
}
set_bit(index, bpmp->threaded.busy);
unlock:
spin_unlock_irqrestore(&bpmp->lock, flags);
return channel;
}
static ssize_t tegra_bpmp_channel_write(struct tegra_bpmp_channel *channel,
unsigned int mrq, unsigned long flags,
const void *data, size_t size)
{
int err;
err = tegra_bpmp_wait_master_free(channel);
if (err < 0)
return err;
return __tegra_bpmp_channel_write(channel, mrq, flags, data, size);
}
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
struct tegra_bpmp_channel *channel;
int err;
if (WARN_ON(!irqs_disabled()))
return -EPERM;
if (!tegra_bpmp_message_valid(msg))
return -EINVAL;
channel = tegra_bpmp_channel_get_tx(bpmp);
err = tegra_bpmp_channel_write(channel, msg->mrq, MSG_ACK,
msg->tx.data, msg->tx.size);
if (err < 0)
return err;
err = mbox_send_message(bpmp->mbox.channel, NULL);
if (err < 0)
return err;
mbox_client_txdone(bpmp->mbox.channel, 0);
err = tegra_bpmp_wait_ack(channel);
if (err < 0)
return err;
return __tegra_bpmp_channel_read(channel, msg->rx.data, msg->rx.size);
}
EXPORT_SYMBOL_GPL(tegra_bpmp_transfer_atomic);
int tegra_bpmp_transfer(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
struct tegra_bpmp_channel *channel;
unsigned long timeout;
int err;
if (WARN_ON(irqs_disabled()))
return -EPERM;
if (!tegra_bpmp_message_valid(msg))
return -EINVAL;
channel = tegra_bpmp_write_threaded(bpmp, msg->mrq, msg->tx.data,
msg->tx.size);
if (IS_ERR(channel))
return PTR_ERR(channel);
err = mbox_send_message(bpmp->mbox.channel, NULL);
if (err < 0)
return err;
mbox_client_txdone(bpmp->mbox.channel, 0);
timeout = usecs_to_jiffies(bpmp->soc->channels.thread.timeout);
err = wait_for_completion_timeout(&channel->completion, timeout);
if (err == 0)
return -ETIMEDOUT;
return tegra_bpmp_channel_read(channel, msg->rx.data, msg->rx.size);
}
EXPORT_SYMBOL_GPL(tegra_bpmp_transfer);
static struct tegra_bpmp_mrq *tegra_bpmp_find_mrq(struct tegra_bpmp *bpmp,
unsigned int mrq)
{
struct tegra_bpmp_mrq *entry;
list_for_each_entry(entry, &bpmp->mrqs, list)
if (entry->mrq == mrq)
return entry;
return NULL;
}
static void tegra_bpmp_mrq_return(struct tegra_bpmp_channel *channel,
int code, const void *data, size_t size)
{
unsigned long flags = channel->ib->flags;
struct tegra_bpmp *bpmp = channel->bpmp;
struct tegra_bpmp_mb_data *frame;
int err;
if (WARN_ON(size > MSG_DATA_MIN_SZ))
return;
err = tegra_ivc_read_advance(channel->ivc);
if (WARN_ON(err < 0))
return;
if ((flags & MSG_ACK) == 0)
return;
frame = tegra_ivc_write_get_next_frame(channel->ivc);
if (WARN_ON(IS_ERR(frame)))
return;
frame->code = code;
if (data && size > 0)
memcpy(frame->data, data, size);
err = tegra_ivc_write_advance(channel->ivc);
if (WARN_ON(err < 0))
return;
if (flags & MSG_RING) {
err = mbox_send_message(bpmp->mbox.channel, NULL);
if (WARN_ON(err < 0))
return;
mbox_client_txdone(bpmp->mbox.channel, 0);
}
}
static void tegra_bpmp_handle_mrq(struct tegra_bpmp *bpmp,
unsigned int mrq,
struct tegra_bpmp_channel *channel)
{
struct tegra_bpmp_mrq *entry;
u32 zero = 0;
spin_lock(&bpmp->lock);
entry = tegra_bpmp_find_mrq(bpmp, mrq);
if (!entry) {
spin_unlock(&bpmp->lock);
tegra_bpmp_mrq_return(channel, -EINVAL, &zero, sizeof(zero));
return;
}
entry->handler(mrq, channel, entry->data);
spin_unlock(&bpmp->lock);
}
int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq,
tegra_bpmp_mrq_handler_t handler, void *data)
{
struct tegra_bpmp_mrq *entry;
unsigned long flags;
if (!handler)
return -EINVAL;
entry = devm_kzalloc(bpmp->dev, sizeof(*entry), GFP_KERNEL);
if (!entry)
return -ENOMEM;
spin_lock_irqsave(&bpmp->lock, flags);
entry->mrq = mrq;
entry->handler = handler;
entry->data = data;
list_add(&entry->list, &bpmp->mrqs);
spin_unlock_irqrestore(&bpmp->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(tegra_bpmp_request_mrq);
void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data)
{
struct tegra_bpmp_mrq *entry;
unsigned long flags;
spin_lock_irqsave(&bpmp->lock, flags);
entry = tegra_bpmp_find_mrq(bpmp, mrq);
if (!entry)
goto unlock;
list_del(&entry->list);
devm_kfree(bpmp->dev, entry);
unlock:
spin_unlock_irqrestore(&bpmp->lock, flags);
}
EXPORT_SYMBOL_GPL(tegra_bpmp_free_mrq);
static void tegra_bpmp_mrq_handle_ping(unsigned int mrq,
struct tegra_bpmp_channel *channel,
void *data)
{
struct mrq_ping_request *request;
struct mrq_ping_response response;
request = (struct mrq_ping_request *)channel->ib->data;
memset(&response, 0, sizeof(response));
response.reply = request->challenge << 1;
tegra_bpmp_mrq_return(channel, 0, &response, sizeof(response));
}
static int tegra_bpmp_ping(struct tegra_bpmp *bpmp)
{
struct mrq_ping_response response;
struct mrq_ping_request request;
struct tegra_bpmp_message msg;
unsigned long flags;
ktime_t start, end;
int err;
memset(&request, 0, sizeof(request));
request.challenge = 1;
memset(&response, 0, sizeof(response));
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_PING;
msg.tx.data = &request;
msg.tx.size = sizeof(request);
msg.rx.data = &response;
msg.rx.size = sizeof(response);
local_irq_save(flags);
start = ktime_get();
err = tegra_bpmp_transfer_atomic(bpmp, &msg);
end = ktime_get();
local_irq_restore(flags);
if (!err)
dev_dbg(bpmp->dev,
"ping ok: challenge: %u, response: %u, time: %lld\n",
request.challenge, response.reply,
ktime_to_us(ktime_sub(end, start)));
return err;
}
static int tegra_bpmp_get_firmware_tag(struct tegra_bpmp *bpmp, char *tag,
size_t size)
{
struct mrq_query_tag_request request;
struct tegra_bpmp_message msg;
unsigned long flags;
dma_addr_t phys;
void *virt;
int err;
virt = dma_alloc_coherent(bpmp->dev, MSG_DATA_MIN_SZ, &phys,
GFP_KERNEL | GFP_DMA32);
if (!virt)
return -ENOMEM;
memset(&request, 0, sizeof(request));
request.addr = phys;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_QUERY_TAG;
msg.tx.data = &request;
msg.tx.size = sizeof(request);
local_irq_save(flags);
err = tegra_bpmp_transfer_atomic(bpmp, &msg);
local_irq_restore(flags);
if (err == 0)
strlcpy(tag, virt, size);
dma_free_coherent(bpmp->dev, MSG_DATA_MIN_SZ, virt, phys);
return err;
}
static void tegra_bpmp_channel_signal(struct tegra_bpmp_channel *channel)
{
unsigned long flags = channel->ob->flags;
if ((flags & MSG_RING) == 0)
return;
complete(&channel->completion);
}
static void tegra_bpmp_handle_rx(struct mbox_client *client, void *data)
{
struct tegra_bpmp *bpmp = mbox_client_to_bpmp(client);
struct tegra_bpmp_channel *channel;
unsigned int i, count;
unsigned long *busy;
channel = tegra_bpmp_channel_get_rx(bpmp);
count = bpmp->soc->channels.thread.count;
busy = bpmp->threaded.busy;
if (tegra_bpmp_master_acked(channel))
tegra_bpmp_handle_mrq(bpmp, channel->ib->code, channel);
spin_lock(&bpmp->lock);
for_each_set_bit(i, busy, count) {
struct tegra_bpmp_channel *channel;
channel = tegra_bpmp_channel_get_thread(bpmp, i);
if (!channel)
continue;
if (tegra_bpmp_master_acked(channel)) {
tegra_bpmp_channel_signal(channel);
clear_bit(i, busy);
}
}
spin_unlock(&bpmp->lock);
}
static void tegra_bpmp_ivc_notify(struct tegra_ivc *ivc, void *data)
{
struct tegra_bpmp *bpmp = data;
int err;
if (WARN_ON(bpmp->mbox.channel == NULL))
return;
err = mbox_send_message(bpmp->mbox.channel, NULL);
if (err < 0)
return;
mbox_client_txdone(bpmp->mbox.channel, 0);
}
static int tegra_bpmp_channel_init(struct tegra_bpmp_channel *channel,
struct tegra_bpmp *bpmp,
unsigned int index)
{
size_t message_size, queue_size;
unsigned int offset;
int err;
channel->ivc = devm_kzalloc(bpmp->dev, sizeof(*channel->ivc),
GFP_KERNEL);
if (!channel->ivc)
return -ENOMEM;
message_size = tegra_ivc_align(MSG_MIN_SZ);
queue_size = tegra_ivc_total_queue_size(message_size);
offset = queue_size * index;
err = tegra_ivc_init(channel->ivc, NULL,
bpmp->rx.virt + offset, bpmp->rx.phys + offset,
bpmp->tx.virt + offset, bpmp->tx.phys + offset,
1, message_size, tegra_bpmp_ivc_notify,
bpmp);
if (err < 0) {
dev_err(bpmp->dev, "failed to setup IVC for channel %u: %d\n",
index, err);
return err;
}
init_completion(&channel->completion);
channel->bpmp = bpmp;
return 0;
}
static void tegra_bpmp_channel_reset(struct tegra_bpmp_channel *channel)
{
/* reset the channel state */
tegra_ivc_reset(channel->ivc);
/* sync the channel state with BPMP */
while (tegra_ivc_notified(channel->ivc))
;
}
static void tegra_bpmp_channel_cleanup(struct tegra_bpmp_channel *channel)
{
tegra_ivc_cleanup(channel->ivc);
}
static int tegra_bpmp_probe(struct platform_device *pdev)
{
struct tegra_bpmp_channel *channel;
struct tegra_bpmp *bpmp;
unsigned int i;
char tag[32];
size_t size;
int err;
bpmp = devm_kzalloc(&pdev->dev, sizeof(*bpmp), GFP_KERNEL);
if (!bpmp)
return -ENOMEM;
bpmp->soc = of_device_get_match_data(&pdev->dev);
bpmp->dev = &pdev->dev;
bpmp->tx.pool = of_gen_pool_get(pdev->dev.of_node, "shmem", 0);
if (!bpmp->tx.pool) {
dev_err(&pdev->dev, "TX shmem pool not found\n");
return -ENOMEM;
}
bpmp->tx.virt = gen_pool_dma_alloc(bpmp->tx.pool, 4096, &bpmp->tx.phys);
if (!bpmp->tx.virt) {
dev_err(&pdev->dev, "failed to allocate from TX pool\n");
return -ENOMEM;
}
bpmp->rx.pool = of_gen_pool_get(pdev->dev.of_node, "shmem", 1);
if (!bpmp->rx.pool) {
dev_err(&pdev->dev, "RX shmem pool not found\n");
err = -ENOMEM;
goto free_tx;
}
bpmp->rx.virt = gen_pool_dma_alloc(bpmp->rx.pool, 4096, &bpmp->rx.phys);
if (!bpmp->rx.pool) {
dev_err(&pdev->dev, "failed to allocate from RX pool\n");
err = -ENOMEM;
goto free_tx;
}
INIT_LIST_HEAD(&bpmp->mrqs);
spin_lock_init(&bpmp->lock);
bpmp->threaded.count = bpmp->soc->channels.thread.count;
sema_init(&bpmp->threaded.lock, bpmp->threaded.count);
size = BITS_TO_LONGS(bpmp->threaded.count) * sizeof(long);
bpmp->threaded.allocated = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
if (!bpmp->threaded.allocated) {
err = -ENOMEM;
goto free_rx;
}
bpmp->threaded.busy = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
if (!bpmp->threaded.busy) {
err = -ENOMEM;
goto free_rx;
}
bpmp->num_channels = bpmp->soc->channels.cpu_tx.count +
bpmp->soc->channels.thread.count +
bpmp->soc->channels.cpu_rx.count;
bpmp->channels = devm_kcalloc(&pdev->dev, bpmp->num_channels,
sizeof(*channel), GFP_KERNEL);
if (!bpmp->channels) {
err = -ENOMEM;
goto free_rx;
}
/* message channel initialization */
for (i = 0; i < bpmp->num_channels; i++) {
struct tegra_bpmp_channel *channel = &bpmp->channels[i];
err = tegra_bpmp_channel_init(channel, bpmp, i);
if (err < 0)
goto cleanup_channels;
}
/* mbox registration */
bpmp->mbox.client.dev = &pdev->dev;
bpmp->mbox.client.rx_callback = tegra_bpmp_handle_rx;
bpmp->mbox.client.tx_block = false;
bpmp->mbox.client.knows_txdone = false;
bpmp->mbox.channel = mbox_request_channel(&bpmp->mbox.client, 0);
if (IS_ERR(bpmp->mbox.channel)) {
err = PTR_ERR(bpmp->mbox.channel);
dev_err(&pdev->dev, "failed to get HSP mailbox: %d\n", err);
goto cleanup_channels;
}
/* reset message channels */
for (i = 0; i < bpmp->num_channels; i++) {
struct tegra_bpmp_channel *channel = &bpmp->channels[i];
tegra_bpmp_channel_reset(channel);
}
err = tegra_bpmp_request_mrq(bpmp, MRQ_PING,
tegra_bpmp_mrq_handle_ping, bpmp);
if (err < 0)
goto free_mbox;
err = tegra_bpmp_ping(bpmp);
if (err < 0) {
dev_err(&pdev->dev, "failed to ping BPMP: %d\n", err);
goto free_mrq;
}
err = tegra_bpmp_get_firmware_tag(bpmp, tag, sizeof(tag) - 1);
if (err < 0) {
dev_err(&pdev->dev, "failed to get firmware tag: %d\n", err);
goto free_mrq;
}
dev_info(&pdev->dev, "firmware: %s\n", tag);
err = of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev);
if (err < 0)
goto free_mrq;
err = tegra_bpmp_init_clocks(bpmp);
if (err < 0)
goto free_mrq;
err = tegra_bpmp_init_resets(bpmp);
if (err < 0)
goto free_mrq;
platform_set_drvdata(pdev, bpmp);
return 0;
free_mrq:
tegra_bpmp_free_mrq(bpmp, MRQ_PING, bpmp);
free_mbox:
mbox_free_channel(bpmp->mbox.channel);
cleanup_channels:
while (i--)
tegra_bpmp_channel_cleanup(&bpmp->channels[i]);
free_rx:
gen_pool_free(bpmp->rx.pool, (unsigned long)bpmp->rx.virt, 4096);
free_tx:
gen_pool_free(bpmp->tx.pool, (unsigned long)bpmp->tx.virt, 4096);
return err;
}
static const struct tegra_bpmp_soc tegra186_soc = {
.channels = {
.cpu_tx = {
.offset = 0,
.count = 6,
.timeout = 60 * USEC_PER_SEC,
},
.thread = {
.offset = 6,
.count = 7,
.timeout = 600 * USEC_PER_SEC,
},
.cpu_rx = {
.offset = 13,
.count = 1,
.timeout = 0,
},
},
.num_resets = 193,
};
static const struct of_device_id tegra_bpmp_match[] = {
{ .compatible = "nvidia,tegra186-bpmp", .data = &tegra186_soc },
{ }
};
static struct platform_driver tegra_bpmp_driver = {
.driver = {
.name = "tegra-bpmp",
.of_match_table = tegra_bpmp_match,
},
.probe = tegra_bpmp_probe,
};
static int __init tegra_bpmp_init(void)
{
return platform_driver_register(&tegra_bpmp_driver);
}
core_initcall(tegra_bpmp_init);

695
drivers/firmware/tegra/ivc.c Normal file
View File

@ -0,0 +1,695 @@
/*
* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <soc/tegra/ivc.h>
#define TEGRA_IVC_ALIGN 64
/*
* IVC channel reset protocol.
*
* Each end uses its tx_channel.state to indicate its synchronization state.
*/
enum tegra_ivc_state {
/*
* This value is zero for backwards compatibility with services that
* assume channels to be initially zeroed. Such channels are in an
* initially valid state, but cannot be asynchronously reset, and must
* maintain a valid state at all times.
*
* The transmitting end can enter the established state from the sync or
* ack state when it observes the receiving endpoint in the ack or
* established state, indicating that has cleared the counters in our
* rx_channel.
*/
TEGRA_IVC_STATE_ESTABLISHED = 0,
/*
* If an endpoint is observed in the sync state, the remote endpoint is
* allowed to clear the counters it owns asynchronously with respect to
* the current endpoint. Therefore, the current endpoint is no longer
* allowed to communicate.
*/
TEGRA_IVC_STATE_SYNC,
/*
* When the transmitting end observes the receiving end in the sync
* state, it can clear the w_count and r_count and transition to the ack
* state. If the remote endpoint observes us in the ack state, it can
* return to the established state once it has cleared its counters.
*/
TEGRA_IVC_STATE_ACK
};
/*
* This structure is divided into two-cache aligned parts, the first is only
* written through the tx.channel pointer, while the second is only written
* through the rx.channel pointer. This delineates ownership of the cache
* lines, which is critical to performance and necessary in non-cache coherent
* implementations.
*/
struct tegra_ivc_header {
union {
struct {
/* fields owned by the transmitting end */
u32 count;
u32 state;
};
u8 pad[TEGRA_IVC_ALIGN];
} tx;
union {
/* fields owned by the receiving end */
u32 count;
u8 pad[TEGRA_IVC_ALIGN];
} rx;
};
static inline void tegra_ivc_invalidate(struct tegra_ivc *ivc, dma_addr_t phys)
{
if (!ivc->peer)
return;
dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN,
DMA_FROM_DEVICE);
}
static inline void tegra_ivc_flush(struct tegra_ivc *ivc, dma_addr_t phys)
{
if (!ivc->peer)
return;
dma_sync_single_for_device(ivc->peer, phys, TEGRA_IVC_ALIGN,
DMA_TO_DEVICE);
}
static inline bool tegra_ivc_empty(struct tegra_ivc *ivc,
struct tegra_ivc_header *header)
{
/*
* This function performs multiple checks on the same values with
* security implications, so create snapshots with ACCESS_ONCE() to
* ensure that these checks use the same values.
*/
u32 tx = ACCESS_ONCE(header->tx.count);
u32 rx = ACCESS_ONCE(header->rx.count);
/*
* Perform an over-full check to prevent denial of service attacks
* where a server could be easily fooled into believing that there's
* an extremely large number of frames ready, since receivers are not
* expected to check for full or over-full conditions.
*
* Although the channel isn't empty, this is an invalid case caused by
* a potentially malicious peer, so returning empty is safer, because
* it gives the impression that the channel has gone silent.
*/
if (tx - rx > ivc->num_frames)
return true;
return tx == rx;
}
static inline bool tegra_ivc_full(struct tegra_ivc *ivc,
struct tegra_ivc_header *header)
{
u32 tx = ACCESS_ONCE(header->tx.count);
u32 rx = ACCESS_ONCE(header->rx.count);
/*
* Invalid cases where the counters indicate that the queue is over
* capacity also appear full.
*/
return tx - rx >= ivc->num_frames;
}
static inline u32 tegra_ivc_available(struct tegra_ivc *ivc,
struct tegra_ivc_header *header)
{
u32 tx = ACCESS_ONCE(header->tx.count);
u32 rx = ACCESS_ONCE(header->rx.count);
/*
* This function isn't expected to be used in scenarios where an
* over-full situation can lead to denial of service attacks. See the
* comment in tegra_ivc_empty() for an explanation about special
* over-full considerations.
*/
return tx - rx;
}
static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc)
{
ACCESS_ONCE(ivc->tx.channel->tx.count) =
ACCESS_ONCE(ivc->tx.channel->tx.count) + 1;
if (ivc->tx.position == ivc->num_frames - 1)
ivc->tx.position = 0;
else
ivc->tx.position++;
}
static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
{
ACCESS_ONCE(ivc->rx.channel->rx.count) =
ACCESS_ONCE(ivc->rx.channel->rx.count) + 1;
if (ivc->rx.position == ivc->num_frames - 1)
ivc->rx.position = 0;
else
ivc->rx.position++;
}
static inline int tegra_ivc_check_read(struct tegra_ivc *ivc)
{
unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
/*
* tx.channel->state is set locally, so it is not synchronized with
* state from the remote peer. The remote peer cannot reset its
* transmit counters until we've acknowledged its synchronization
* request, so no additional synchronization is required because an
* asynchronous transition of rx.channel->state to
* TEGRA_IVC_STATE_ACK is not allowed.
*/
if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
return -ECONNRESET;
/*
* Avoid unnecessary invalidations when performing repeated accesses
* to an IVC channel by checking the old queue pointers first.
*
* Synchronization is only necessary when these pointers indicate
* empty or full.
*/
if (!tegra_ivc_empty(ivc, ivc->rx.channel))
return 0;
tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
if (tegra_ivc_empty(ivc, ivc->rx.channel))
return -ENOSPC;
return 0;
}
static inline int tegra_ivc_check_write(struct tegra_ivc *ivc)
{
unsigned int offset = offsetof(struct tegra_ivc_header, rx.count);
if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
return -ECONNRESET;
if (!tegra_ivc_full(ivc, ivc->tx.channel))
return 0;
tegra_ivc_invalidate(ivc, ivc->tx.phys + offset);
if (tegra_ivc_full(ivc, ivc->tx.channel))
return -ENOSPC;
return 0;
}
static void *tegra_ivc_frame_virt(struct tegra_ivc *ivc,
struct tegra_ivc_header *header,
unsigned int frame)
{
if (WARN_ON(frame >= ivc->num_frames))
return ERR_PTR(-EINVAL);
return (void *)(header + 1) + ivc->frame_size * frame;
}
static inline dma_addr_t tegra_ivc_frame_phys(struct tegra_ivc *ivc,
dma_addr_t phys,
unsigned int frame)
{
unsigned long offset;
offset = sizeof(struct tegra_ivc_header) + ivc->frame_size * frame;
return phys + offset;
}
static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc,
dma_addr_t phys,
unsigned int frame,
unsigned int offset,
size_t size)
{
if (!ivc->peer || WARN_ON(frame >= ivc->num_frames))
return;
phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset;
dma_sync_single_for_cpu(ivc->peer, phys, size, DMA_FROM_DEVICE);
}
static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc,
dma_addr_t phys,
unsigned int frame,
unsigned int offset,
size_t size)
{
if (!ivc->peer || WARN_ON(frame >= ivc->num_frames))
return;
phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset;
dma_sync_single_for_device(ivc->peer, phys, size, DMA_TO_DEVICE);
}
/* directly peek at the next frame rx'ed */
void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc)
{
int err;
if (WARN_ON(ivc == NULL))
return ERR_PTR(-EINVAL);
err = tegra_ivc_check_read(ivc);
if (err < 0)
return ERR_PTR(err);
/*
* Order observation of ivc->rx.position potentially indicating new
* data before data read.
*/
smp_rmb();
tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0,
ivc->frame_size);
return tegra_ivc_frame_virt(ivc, ivc->rx.channel, ivc->rx.position);
}
EXPORT_SYMBOL(tegra_ivc_read_get_next_frame);
int tegra_ivc_read_advance(struct tegra_ivc *ivc)
{
unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
int err;
/*
* No read barriers or synchronization here: the caller is expected to
* have already observed the channel non-empty. This check is just to
* catch programming errors.
*/
err = tegra_ivc_check_read(ivc);
if (err < 0)
return err;
tegra_ivc_advance_rx(ivc);
tegra_ivc_flush(ivc, ivc->rx.phys + rx);
/*
* Ensure our write to ivc->rx.position occurs before our read from
* ivc->tx.position.
*/
smp_mb();
/*
* Notify only upon transition from full to non-full. The available
* count can only asynchronously increase, so the worst possible
* side-effect will be a spurious notification.
*/
tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);
if (tegra_ivc_available(ivc, ivc->rx.channel) == ivc->num_frames - 1)
ivc->notify(ivc, ivc->notify_data);
return 0;
}
EXPORT_SYMBOL(tegra_ivc_read_advance);
/* directly poke at the next frame to be tx'ed */
void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc)
{
int err;
err = tegra_ivc_check_write(ivc);
if (err < 0)
return ERR_PTR(err);
return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position);
}
EXPORT_SYMBOL(tegra_ivc_write_get_next_frame);
/* advance the tx buffer */
int tegra_ivc_write_advance(struct tegra_ivc *ivc)
{
unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
int err;
err = tegra_ivc_check_write(ivc);
if (err < 0)
return err;
tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0,
ivc->frame_size);
/*
* Order any possible stores to the frame before update of
* ivc->tx.position.
*/
smp_wmb();
tegra_ivc_advance_tx(ivc);
tegra_ivc_flush(ivc, ivc->tx.phys + tx);
/*
* Ensure our write to ivc->tx.position occurs before our read from
* ivc->rx.position.
*/
smp_mb();
/*
* Notify only upon transition from empty to non-empty. The available
* count can only asynchronously decrease, so the worst possible
* side-effect will be a spurious notification.
*/
tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);
if (tegra_ivc_available(ivc, ivc->tx.channel) == 1)
ivc->notify(ivc, ivc->notify_data);
return 0;
}
EXPORT_SYMBOL(tegra_ivc_write_advance);
void tegra_ivc_reset(struct tegra_ivc *ivc)
{
unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC;
tegra_ivc_flush(ivc, ivc->tx.phys + offset);
ivc->notify(ivc, ivc->notify_data);
}
EXPORT_SYMBOL(tegra_ivc_reset);
/*
* =======================================================
* IVC State Transition Table - see tegra_ivc_notified()
* =======================================================
*
* local remote action
* ----- ------ -----------------------------------
* SYNC EST <none>
* SYNC ACK reset counters; move to EST; notify
* SYNC SYNC reset counters; move to ACK; notify
* ACK EST move to EST; notify
* ACK ACK move to EST; notify
* ACK SYNC reset counters; move to ACK; notify
* EST EST <none>
* EST ACK <none>
* EST SYNC reset counters; move to ACK; notify
*
* ===============================================================
*/
int tegra_ivc_notified(struct tegra_ivc *ivc)
{
unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
enum tegra_ivc_state state;
/* Copy the receiver's state out of shared memory. */
tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
state = ACCESS_ONCE(ivc->rx.channel->tx.state);
if (state == TEGRA_IVC_STATE_SYNC) {
offset = offsetof(struct tegra_ivc_header, tx.count);
/*
* Order observation of TEGRA_IVC_STATE_SYNC before stores
* clearing tx.channel.
*/
smp_rmb();
/*
* Reset tx.channel counters. The remote end is in the SYNC
* state and won't make progress until we change our state,
* so the counters are not in use at this time.
*/
ivc->tx.channel->tx.count = 0;
ivc->rx.channel->rx.count = 0;
ivc->tx.position = 0;
ivc->rx.position = 0;
/*
* Ensure that counters appear cleared before new state can be
* observed.
*/
smp_wmb();
/*
* Move to ACK state. We have just cleared our counters, so it
* is now safe for the remote end to start using these values.
*/
ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK;
tegra_ivc_flush(ivc, ivc->tx.phys + offset);
/*
* Notify remote end to observe state transition.
*/
ivc->notify(ivc, ivc->notify_data);
} else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC &&
state == TEGRA_IVC_STATE_ACK) {
offset = offsetof(struct tegra_ivc_header, tx.count);
/*
* Order observation of ivc_state_sync before stores clearing
* tx_channel.
*/
smp_rmb();
/*
* Reset tx.channel counters. The remote end is in the ACK
* state and won't make progress until we change our state,
* so the counters are not in use at this time.
*/
ivc->tx.channel->tx.count = 0;
ivc->rx.channel->rx.count = 0;
ivc->tx.position = 0;
ivc->rx.position = 0;
/*
* Ensure that counters appear cleared before new state can be
* observed.
*/
smp_wmb();
/*
* Move to ESTABLISHED state. We know that the remote end has
* already cleared its counters, so it is safe to start
* writing/reading on this channel.
*/
ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED;
tegra_ivc_flush(ivc, ivc->tx.phys + offset);
/*
* Notify remote end to observe state transition.
*/
ivc->notify(ivc, ivc->notify_data);
} else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) {
offset = offsetof(struct tegra_ivc_header, tx.count);
/*
* At this point, we have observed the peer to be in either
* the ACK or ESTABLISHED state. Next, order observation of
* peer state before storing to tx.channel.
*/
smp_rmb();
/*
* Move to ESTABLISHED state. We know that we have previously
* cleared our counters, and we know that the remote end has
* cleared its counters, so it is safe to start writing/reading
* on this channel.
*/
ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED;
tegra_ivc_flush(ivc, ivc->tx.phys + offset);
/*
* Notify remote end to observe state transition.
*/
ivc->notify(ivc, ivc->notify_data);
} else {
/*
* There is no need to handle any further action. Either the
* channel is already fully established, or we are waiting for
* the remote end to catch up with our current state. Refer
* to the diagram in "IVC State Transition Table" above.
*/
}
if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
return -EAGAIN;
return 0;
}
EXPORT_SYMBOL(tegra_ivc_notified);
size_t tegra_ivc_align(size_t size)
{
return ALIGN(size, TEGRA_IVC_ALIGN);
}
EXPORT_SYMBOL(tegra_ivc_align);
unsigned tegra_ivc_total_queue_size(unsigned queue_size)
{
if (!IS_ALIGNED(queue_size, TEGRA_IVC_ALIGN)) {
pr_err("%s: queue_size (%u) must be %u-byte aligned\n",
__func__, queue_size, TEGRA_IVC_ALIGN);
return 0;
}
return queue_size + sizeof(struct tegra_ivc_header);
}
EXPORT_SYMBOL(tegra_ivc_total_queue_size);
static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,
unsigned int num_frames, size_t frame_size)
{
BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count),
TEGRA_IVC_ALIGN));
BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, rx.count),
TEGRA_IVC_ALIGN));
BUILD_BUG_ON(!IS_ALIGNED(sizeof(struct tegra_ivc_header),
TEGRA_IVC_ALIGN));
if ((uint64_t)num_frames * (uint64_t)frame_size >= 0x100000000UL) {
pr_err("num_frames * frame_size overflows\n");
return -EINVAL;
}
if (!IS_ALIGNED(frame_size, TEGRA_IVC_ALIGN)) {
pr_err("frame size not adequately aligned: %zu\n", frame_size);
return -EINVAL;
}
/*
* The headers must at least be aligned enough for counters
* to be accessed atomically.
*/
if (!IS_ALIGNED(rx, TEGRA_IVC_ALIGN)) {
pr_err("IVC channel start not aligned: %#lx\n", rx);
return -EINVAL;
}
if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) {
pr_err("IVC channel start not aligned: %#lx\n", tx);
return -EINVAL;
}
if (rx < tx) {
if (rx + frame_size * num_frames > tx) {
pr_err("queue regions overlap: %#lx + %zx > %#lx\n",
rx, frame_size * num_frames, tx);
return -EINVAL;
}
} else {
if (tx + frame_size * num_frames > rx) {
pr_err("queue regions overlap: %#lx + %zx > %#lx\n",
tx, frame_size * num_frames, rx);
return -EINVAL;
}
}
return 0;
}
int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx,
dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys,
unsigned int num_frames, size_t frame_size,
void (*notify)(struct tegra_ivc *ivc, void *data),
void *data)
{
size_t queue_size;
int err;
if (WARN_ON(!ivc || !notify))
return -EINVAL;
/*
* All sizes that can be returned by communication functions should
* fit in an int.
*/
if (frame_size > INT_MAX)
return -E2BIG;
err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx,
num_frames, frame_size);
if (err < 0)
return err;
queue_size = tegra_ivc_total_queue_size(num_frames * frame_size);
if (peer) {
ivc->rx.phys = dma_map_single(peer, rx, queue_size,
DMA_BIDIRECTIONAL);
if (ivc->rx.phys == DMA_ERROR_CODE)
return -ENOMEM;
ivc->tx.phys = dma_map_single(peer, tx, queue_size,
DMA_BIDIRECTIONAL);
if (ivc->tx.phys == DMA_ERROR_CODE) {
dma_unmap_single(peer, ivc->rx.phys, queue_size,
DMA_BIDIRECTIONAL);
return -ENOMEM;
}
} else {
ivc->rx.phys = rx_phys;
ivc->tx.phys = tx_phys;
}
ivc->rx.channel = rx;
ivc->tx.channel = tx;
ivc->peer = peer;
ivc->notify = notify;
ivc->notify_data = data;
ivc->frame_size = frame_size;
ivc->num_frames = num_frames;
/*
* These values aren't necessarily correct until the channel has been
* reset.
*/
ivc->tx.position = 0;
ivc->rx.position = 0;
return 0;
}
EXPORT_SYMBOL(tegra_ivc_init);
void tegra_ivc_cleanup(struct tegra_ivc *ivc)
{
if (ivc->peer) {
size_t size = tegra_ivc_total_queue_size(ivc->num_frames *
ivc->frame_size);
dma_unmap_single(ivc->peer, ivc->rx.phys, size,
DMA_BIDIRECTIONAL);
dma_unmap_single(ivc->peer, ivc->tx.phys, size,
DMA_BIDIRECTIONAL);
}
}
EXPORT_SYMBOL(tegra_ivc_cleanup);

1991
drivers/firmware/ti_sci.c Normal file
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492
drivers/firmware/ti_sci.h Normal file
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@ -0,0 +1,492 @@
/*
* Texas Instruments System Control Interface (TISCI) Protocol
*
* Communication protocol with TI SCI hardware
* The system works in a message response protocol
* See: http://processors.wiki.ti.com/index.php/TISCI for details
*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __TI_SCI_H
#define __TI_SCI_H
/* Generic Messages */
#define TI_SCI_MSG_ENABLE_WDT 0x0000
#define TI_SCI_MSG_WAKE_RESET 0x0001
#define TI_SCI_MSG_VERSION 0x0002
#define TI_SCI_MSG_WAKE_REASON 0x0003
#define TI_SCI_MSG_GOODBYE 0x0004
#define TI_SCI_MSG_SYS_RESET 0x0005
/* Device requests */
#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
/* Clock requests */
#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
/**
* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
* @type: Type of messages: One of TI_SCI_MSG* values
* @host: Host of the message
* @seq: Message identifier indicating a transfer sequence
* @flags: Flag for the message
*/
struct ti_sci_msg_hdr {
u16 type;
u8 host;
u8 seq;
#define TI_SCI_MSG_FLAG(val) (1 << (val))
#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
/* Additional Flags */
u32 flags;
} __packed;
/**
* struct ti_sci_msg_resp_version - Response for a message
* @hdr: Generic header
* @firmware_description: String describing the firmware
* @firmware_revision: Firmware revision
* @abi_major: Major version of the ABI that firmware supports
* @abi_minor: Minor version of the ABI that firmware supports
*
* In general, ABI version changes follow the rule that minor version increments
* are backward compatible. Major revision changes in ABI may not be
* backward compatible.
*
* Response to a generic message with message type TI_SCI_MSG_VERSION
*/
struct ti_sci_msg_resp_version {
struct ti_sci_msg_hdr hdr;
char firmware_description[32];
u16 firmware_revision;
u8 abi_major;
u8 abi_minor;
} __packed;
/**
* struct ti_sci_msg_req_reboot - Reboot the SoC
* @hdr: Generic Header
*
* Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_reboot {
struct ti_sci_msg_hdr hdr;
} __packed;
/**
* struct ti_sci_msg_req_set_device_state - Set the desired state of the device
* @hdr: Generic header
* @id: Indicates which device to modify
* @reserved: Reserved space in message, must be 0 for backward compatibility
* @state: The desired state of the device.
*
* Certain flags can also be set to alter the device state:
* + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
* The meaning of this flag will vary slightly from device to device and from
* SoC to SoC but it generally allows the device to wake the SoC out of deep
* suspend states.
* + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
* + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
* with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
* If another host already has this device set to STATE_RETENTION or STATE_ON,
* the message will fail. Once successful, other hosts attempting to set
* STATE_RETENTION or STATE_ON will fail.
*
* Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_set_device_state {
/* Additional hdr->flags options */
#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
struct ti_sci_msg_hdr hdr;
u32 id;
u32 reserved;
#define MSG_DEVICE_SW_STATE_AUTO_OFF 0
#define MSG_DEVICE_SW_STATE_RETENTION 1
#define MSG_DEVICE_SW_STATE_ON 2
u8 state;
} __packed;
/**
* struct ti_sci_msg_req_get_device_state - Request to get device.
* @hdr: Generic header
* @id: Device Identifier
*
* Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
* information
*/
struct ti_sci_msg_req_get_device_state {
struct ti_sci_msg_hdr hdr;
u32 id;
} __packed;
/**
* struct ti_sci_msg_resp_get_device_state - Response to get device request.
* @hdr: Generic header
* @context_loss_count: Indicates how many times the device has lost context. A
* driver can use this monotonic counter to determine if the device has
* lost context since the last time this message was exchanged.
* @resets: Programmed state of the reset lines.
* @programmed_state: The state as programmed by set_device.
* - Uses the MSG_DEVICE_SW_* macros
* @current_state: The actual state of the hardware.
*
* Response to request TI_SCI_MSG_GET_DEVICE_STATE.
*/
struct ti_sci_msg_resp_get_device_state {
struct ti_sci_msg_hdr hdr;
u32 context_loss_count;
u32 resets;
u8 programmed_state;
#define MSG_DEVICE_HW_STATE_OFF 0
#define MSG_DEVICE_HW_STATE_ON 1
#define MSG_DEVICE_HW_STATE_TRANS 2
u8 current_state;
} __packed;
/**
* struct ti_sci_msg_req_set_device_resets - Set the desired resets
* configuration of the device
* @hdr: Generic header
* @id: Indicates which device to modify
* @resets: A bit field of resets for the device. The meaning, behavior,
* and usage of the reset flags are device specific. 0 for a bit
* indicates releasing the reset represented by that bit while 1
* indicates keeping it held.
*
* Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_set_device_resets {
struct ti_sci_msg_hdr hdr;
u32 id;
u32 resets;
} __packed;
/**
* struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
* @hdr: Generic Header, Certain flags can be set specific to the clocks:
* MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
* via spread spectrum clocking.
* MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
* frequency to be changed while it is running so long as it
* is within the min/max limits.
* MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
* is only applicable to clock inputs on the SoC pseudo-device.
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to modify.
* @request_state: Request the state for the clock to be set to.
* MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
* it can be disabled, regardless of the state of the device
* MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
* automatically manage the state of this clock. If the device
* is enabled, then the clock is enabled. If the device is set
* to off or retention, then the clock is internally set as not
* being required by the device.(default)
* MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
* regardless of the state of the device.
*
* Normally, all required clocks are managed by TISCI entity, this is used
* only for specific control *IF* required. Auto managed state is
* MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
* will explicitly control.
*
* Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
* ACK or NACK message.
*/
struct ti_sci_msg_req_set_clock_state {
/* Additional hdr->flags options */
#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
#define MSG_CLOCK_SW_STATE_UNREQ 0
#define MSG_CLOCK_SW_STATE_AUTO 1
#define MSG_CLOCK_SW_STATE_REQ 2
u8 request_state;
} __packed;
/**
* struct ti_sci_msg_req_get_clock_state - Request for clock state
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to get state of.
*
* Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
* of the clock
*/
struct ti_sci_msg_req_get_clock_state {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_resp_get_clock_state - Response to get clock state
* @hdr: Generic Header
* @programmed_state: Any programmed state of the clock. This is one of
* MSG_CLOCK_SW_STATE* values.
* @current_state: Current state of the clock. This is one of:
* MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
* MSG_CLOCK_HW_STATE_READY: Clock is ready
*
* Response to TI_SCI_MSG_GET_CLOCK_STATE.
*/
struct ti_sci_msg_resp_get_clock_state {
struct ti_sci_msg_hdr hdr;
u8 programmed_state;
#define MSG_CLOCK_HW_STATE_NOT_READY 0
#define MSG_CLOCK_HW_STATE_READY 1
u8 current_state;
} __packed;
/**
* struct ti_sci_msg_req_set_clock_parent - Set the clock parent
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to modify.
* @parent_id: The new clock parent is selectable by an index via this
* parameter.
*
* Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
* ACK / NACK message.
*/
struct ti_sci_msg_req_set_clock_parent {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
u8 parent_id;
} __packed;
/**
* struct ti_sci_msg_req_get_clock_parent - Get the clock parent
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to get the parent for.
*
* Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
*/
struct ti_sci_msg_req_get_clock_parent {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
* @hdr: Generic Header
* @parent_id: The current clock parent
*
* Response to TI_SCI_MSG_GET_CLOCK_PARENT.
*/
struct ti_sci_msg_resp_get_clock_parent {
struct ti_sci_msg_hdr hdr;
u8 parent_id;
} __packed;
/**
* struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
* @hdr: Generic header
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
*
* This request provides information about how many clock parent options
* are available for a given clock to a device. This is typically used
* for input clocks.
*
* Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
* message, or NACK in case of inability to satisfy request.
*/
struct ti_sci_msg_req_get_clock_num_parents {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
* @hdr: Generic header
* @num_parents: Number of clock parents
*
* Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
*/
struct ti_sci_msg_resp_get_clock_num_parents {
struct ti_sci_msg_hdr hdr;
u8 num_parents;
} __packed;
/**
* struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* @target_freq_hz: The target clock frequency. A frequency will be found
* as close to this target frequency as possible.
* @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* @clk_id: Clock identifier for the device for this request.
*
* NOTE: Normally clock frequency management is automatically done by TISCI
* entity. In case of specific requests, TISCI evaluates capability to achieve
* requested frequency within provided range and responds with
* result message.
*
* Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
* or NACK in case of inability to satisfy request.
*/
struct ti_sci_msg_req_query_clock_freq {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u64 min_freq_hz;
u64 target_freq_hz;
u64 max_freq_hz;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
* @hdr: Generic Header
* @freq_hz: Frequency that is the best match in Hz.
*
* Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
* cannot be satisfied, the message will be of type NACK.
*/
struct ti_sci_msg_resp_query_clock_freq {
struct ti_sci_msg_hdr hdr;
u64 freq_hz;
} __packed;
/**
* struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* @target_freq_hz: The target clock frequency. The clock will be programmed
* at a rate as close to this target frequency as possible.
* @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* @clk_id: Clock identifier for the device for this request.
*
* NOTE: Normally clock frequency management is automatically done by TISCI
* entity. In case of specific requests, TISCI evaluates capability to achieve
* requested range and responds with success/failure message.
*
* This sets the desired frequency for a clock within an allowable
* range. This message will fail on an enabled clock unless
* MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
* if other clocks have their frequency modified due to this message,
* they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
*
* Calling set frequency on a clock input to the SoC pseudo-device will
* inform the PMMC of that clock's frequency. Setting a frequency of
* zero will indicate the clock is disabled.
*
* Calling set frequency on clock outputs from the SoC pseudo-device will
* function similarly to setting the clock frequency on a device.
*
* Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
* message.
*/
struct ti_sci_msg_req_set_clock_freq {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u64 min_freq_hz;
u64 target_freq_hz;
u64 max_freq_hz;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
* @hdr: Generic Header
* @dev_id: Device identifier this request is for
* @clk_id: Clock identifier for the device for this request.
*
* NOTE: Normally clock frequency management is automatically done by TISCI
* entity. In some cases, clock frequencies are configured by host.
*
* Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
* that the clock is currently at.
*/
struct ti_sci_msg_req_get_clock_freq {
struct ti_sci_msg_hdr hdr;
u32 dev_id;
u8 clk_id;
} __packed;
/**
* struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
* @hdr: Generic Header
* @freq_hz: Frequency that the clock is currently on, in Hz.
*
* Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
*/
struct ti_sci_msg_resp_get_clock_freq {
struct ti_sci_msg_hdr hdr;
u64 freq_hz;
} __packed;
#endif /* __TI_SCI_H */

9
drivers/mailbox/Kconfig
View File

@ -124,6 +124,15 @@ config MAILBOX_TEST
Test client to help with testing new Controller driver
implementations.
config TEGRA_HSP_MBOX
bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
depends on ARCH_TEGRA_186_SOC
help
The Tegra HSP driver is used for the interprocessor communication
between different remote processors and host processors on Tegra186
and later SoCs. Say Y here if you want to have this support.
If unsure say N.
config XGENE_SLIMPRO_MBOX
tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
depends on ARCH_XGENE

2
drivers/mailbox/Makefile
View File

@ -29,3 +29,5 @@ obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o

479
drivers/mailbox/tegra-hsp.c Normal file
View File

@ -0,0 +1,479 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mailbox_controller.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#define HSP_INT_DIMENSIONING 0x380
#define HSP_nSM_SHIFT 0
#define HSP_nSS_SHIFT 4
#define HSP_nAS_SHIFT 8
#define HSP_nDB_SHIFT 12
#define HSP_nSI_SHIFT 16
#define HSP_nINT_MASK 0xf
#define HSP_DB_TRIGGER 0x0
#define HSP_DB_ENABLE 0x4
#define HSP_DB_RAW 0x8
#define HSP_DB_PENDING 0xc
#define HSP_DB_CCPLEX 1
#define HSP_DB_BPMP 3
#define HSP_DB_MAX 7
struct tegra_hsp_channel;
struct tegra_hsp;
struct tegra_hsp_channel {
struct tegra_hsp *hsp;
struct mbox_chan *chan;
void __iomem *regs;
};
struct tegra_hsp_doorbell {
struct tegra_hsp_channel channel;
struct list_head list;
const char *name;
unsigned int master;
unsigned int index;
};
struct tegra_hsp_db_map {
const char *name;
unsigned int master;
unsigned int index;
};
struct tegra_hsp_soc {
const struct tegra_hsp_db_map *map;
};
struct tegra_hsp {
const struct tegra_hsp_soc *soc;
struct mbox_controller mbox;
void __iomem *regs;
unsigned int irq;
unsigned int num_sm;
unsigned int num_as;
unsigned int num_ss;
unsigned int num_db;
unsigned int num_si;
spinlock_t lock;
struct list_head doorbells;
};
static inline struct tegra_hsp *
to_tegra_hsp(struct mbox_controller *mbox)
{
return container_of(mbox, struct tegra_hsp, mbox);
}
static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
{
return readl(hsp->regs + offset);
}
static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
unsigned int offset)
{
writel(value, hsp->regs + offset);
}
static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
unsigned int offset)
{
return readl(channel->regs + offset);
}
static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
u32 value, unsigned int offset)
{
writel(value, channel->regs + offset);
}
static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
{
u32 value;
value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
}
static struct tegra_hsp_doorbell *
__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
{
struct tegra_hsp_doorbell *entry;
list_for_each_entry(entry, &hsp->doorbells, list)
if (entry->master == master)
return entry;
return NULL;
}
static struct tegra_hsp_doorbell *
tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
{
struct tegra_hsp_doorbell *db;
unsigned long flags;
spin_lock_irqsave(&hsp->lock, flags);
db = __tegra_hsp_doorbell_get(hsp, master);
spin_unlock_irqrestore(&hsp->lock, flags);
return db;
}
static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
{
struct tegra_hsp *hsp = data;
struct tegra_hsp_doorbell *db;
unsigned long master, value;
db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
if (!db)
return IRQ_NONE;
value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
spin_lock(&hsp->lock);
for_each_set_bit(master, &value, hsp->mbox.num_chans) {
struct tegra_hsp_doorbell *db;
db = __tegra_hsp_doorbell_get(hsp, master);
/*
* Depending on the bootloader chain, the CCPLEX doorbell will
* have some doorbells enabled, which means that requesting an
* interrupt will immediately fire.
*
* In that case, db->channel.chan will still be NULL here and
* cause a crash if not properly guarded.
*
* It remains to be seen if ignoring the doorbell in that case
* is the correct solution.
*/
if (db && db->channel.chan)
mbox_chan_received_data(db->channel.chan, NULL);
}
spin_unlock(&hsp->lock);
return IRQ_HANDLED;
}
static struct tegra_hsp_channel *
tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
unsigned int master, unsigned int index)
{
struct tegra_hsp_doorbell *db;
unsigned int offset;
unsigned long flags;
db = kzalloc(sizeof(*db), GFP_KERNEL);
if (!db)
return ERR_PTR(-ENOMEM);
offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16;
offset += index * 0x100;
db->channel.regs = hsp->regs + offset;
db->channel.hsp = hsp;
db->name = kstrdup_const(name, GFP_KERNEL);
db->master = master;
db->index = index;
spin_lock_irqsave(&hsp->lock, flags);
list_add_tail(&db->list, &hsp->doorbells);
spin_unlock_irqrestore(&hsp->lock, flags);
return &db->channel;
}
static void __tegra_hsp_doorbell_destroy(struct tegra_hsp_doorbell *db)
{
list_del(&db->list);
kfree_const(db->name);
kfree(db);
}
static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
{
struct tegra_hsp_doorbell *db = chan->con_priv;
tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
return 0;
}
static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
{
struct tegra_hsp_doorbell *db = chan->con_priv;
struct tegra_hsp *hsp = db->channel.hsp;
struct tegra_hsp_doorbell *ccplex;
unsigned long flags;
u32 value;
if (db->master >= hsp->mbox.num_chans) {
dev_err(hsp->mbox.dev,
"invalid master ID %u for HSP channel\n",
db->master);
return -EINVAL;
}
ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
if (!ccplex)
return -ENODEV;
if (!tegra_hsp_doorbell_can_ring(db))
return -ENODEV;
spin_lock_irqsave(&hsp->lock, flags);
value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
value |= BIT(db->master);
tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
spin_unlock_irqrestore(&hsp->lock, flags);
return 0;
}
static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
{
struct tegra_hsp_doorbell *db = chan->con_priv;
struct tegra_hsp *hsp = db->channel.hsp;
struct tegra_hsp_doorbell *ccplex;
unsigned long flags;
u32 value;
ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
if (!ccplex)
return;
spin_lock_irqsave(&hsp->lock, flags);
value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
value &= ~BIT(db->master);
tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
spin_unlock_irqrestore(&hsp->lock, flags);
}
static const struct mbox_chan_ops tegra_hsp_doorbell_ops = {
.send_data = tegra_hsp_doorbell_send_data,
.startup = tegra_hsp_doorbell_startup,
.shutdown = tegra_hsp_doorbell_shutdown,
};
static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox,
const struct of_phandle_args *args)
{
struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
struct tegra_hsp *hsp = to_tegra_hsp(mbox);
unsigned int type = args->args[0];
unsigned int master = args->args[1];
struct tegra_hsp_doorbell *db;
struct mbox_chan *chan;
unsigned long flags;
unsigned int i;
switch (type) {
case TEGRA_HSP_MBOX_TYPE_DB:
db = tegra_hsp_doorbell_get(hsp, master);
if (db)
channel = &db->channel;
break;
default:
break;
}
if (IS_ERR(channel))
return ERR_CAST(channel);
spin_lock_irqsave(&hsp->lock, flags);
for (i = 0; i < hsp->mbox.num_chans; i++) {
chan = &hsp->mbox.chans[i];
if (!chan->con_priv) {
chan->con_priv = channel;
channel->chan = chan;
break;
}
chan = NULL;
}
spin_unlock_irqrestore(&hsp->lock, flags);
return chan ?: ERR_PTR(-EBUSY);
}
static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp)
{
struct tegra_hsp_doorbell *db, *tmp;
unsigned long flags;
spin_lock_irqsave(&hsp->lock, flags);
list_for_each_entry_safe(db, tmp, &hsp->doorbells, list)
__tegra_hsp_doorbell_destroy(db);
spin_unlock_irqrestore(&hsp->lock, flags);
}
static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
{
const struct tegra_hsp_db_map *map = hsp->soc->map;
struct tegra_hsp_channel *channel;
while (map->name) {
channel = tegra_hsp_doorbell_create(hsp, map->name,
map->master, map->index);
if (IS_ERR(channel)) {
tegra_hsp_remove_doorbells(hsp);
return PTR_ERR(channel);
}
map++;
}
return 0;
}
static int tegra_hsp_probe(struct platform_device *pdev)
{
struct tegra_hsp *hsp;
struct resource *res;
u32 value;
int err;
hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
if (!hsp)
return -ENOMEM;
hsp->soc = of_device_get_match_data(&pdev->dev);
INIT_LIST_HEAD(&hsp->doorbells);
spin_lock_init(&hsp->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
hsp->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hsp->regs))
return PTR_ERR(hsp->regs);
value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
err = platform_get_irq_byname(pdev, "doorbell");
if (err < 0) {
dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err);
return err;
}
hsp->irq = err;
hsp->mbox.of_xlate = of_tegra_hsp_xlate;
hsp->mbox.num_chans = 32;
hsp->mbox.dev = &pdev->dev;
hsp->mbox.txdone_irq = false;
hsp->mbox.txdone_poll = false;
hsp->mbox.ops = &tegra_hsp_doorbell_ops;
hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans,
sizeof(*hsp->mbox.chans),
GFP_KERNEL);
if (!hsp->mbox.chans)
return -ENOMEM;
err = tegra_hsp_add_doorbells(hsp);
if (err < 0) {
dev_err(&pdev->dev, "failed to add doorbells: %d\n", err);
return err;
}
platform_set_drvdata(pdev, hsp);
err = mbox_controller_register(&hsp->mbox);
if (err) {
dev_err(&pdev->dev, "failed to register mailbox: %d\n", err);
tegra_hsp_remove_doorbells(hsp);
return err;
}
err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq,
IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
hsp->irq, err);
return err;
}
return 0;
}
static int tegra_hsp_remove(struct platform_device *pdev)
{
struct tegra_hsp *hsp = platform_get_drvdata(pdev);
mbox_controller_unregister(&hsp->mbox);
tegra_hsp_remove_doorbells(hsp);
return 0;
}
static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
{ "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
{ "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
{ /* sentinel */ }
};
static const struct tegra_hsp_soc tegra186_hsp_soc = {
.map = tegra186_hsp_db_map,
};
static const struct of_device_id tegra_hsp_match[] = {
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
{ }
};
static struct platform_driver tegra_hsp_driver = {
.driver = {
.name = "tegra-hsp",
.of_match_table = tegra_hsp_match,
},
.probe = tegra_hsp_probe,
.remove = tegra_hsp_remove,
};
static int __init tegra_hsp_init(void)
{
return platform_driver_register(&tegra_hsp_driver);
}
core_initcall(tegra_hsp_init);

8
drivers/memory/Kconfig
View File

@ -134,6 +134,14 @@ config MTK_SMI
mainly help enable/disable iommu and control the power domain and
clocks for each local arbiter.
config DA8XX_DDRCTL
bool "Texas Instruments da8xx DDR2/mDDR driver"
depends on ARCH_DAVINCI_DA8XX
help
This driver is for the DDR2/mDDR Memory Controller present on
Texas Instruments da8xx SoCs. It's used to tweak various memory
controller configuration options.
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"

1
drivers/memory/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
obj-$(CONFIG_MTK_SMI) += mtk-smi.o
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/

2
drivers/memory/atmel-ebi.c
View File

@ -657,7 +657,7 @@ static int at91_ebi_dev_disable(struct at91_ebi *ebi, struct device_node *np)
return -ENOMEM;
newprop->value = devm_kstrdup(dev, "disabled", GFP_KERNEL);
if (!newprop->name)
if (!newprop->value)
return -ENOMEM;
newprop->length = sizeof("disabled");

6
drivers/memory/atmel-sdramc.c
View File

@ -85,8 +85,4 @@ static struct platform_driver atmel_ramc_driver = {
},
};
static int __init atmel_ramc_init(void)
{
return platform_driver_register(&atmel_ramc_driver);
}
device_initcall(atmel_ramc_init);
builtin_platform_driver(atmel_ramc_driver);

173
drivers/memory/da8xx-ddrctl.c Normal file
View File

@ -0,0 +1,173 @@
/*
* TI da8xx DDR2/mDDR controller driver
*
* Copyright (C) 2016 BayLibre SAS
*
* Author:
* Bartosz Golaszewski <bgolaszewski@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/io.h>
/*
* REVISIT: Linux doesn't have a good framework for the kind of performance
* knobs this driver controls. We can't use device tree properties as it deals
* with hardware configuration rather than description. We also don't want to
* commit to maintaining some random sysfs attributes.
*
* For now we just hardcode the register values for the boards that need
* some changes (as is the case for the LCD controller on da850-lcdk - the
* first board we support here). When linux gets an appropriate framework,
* we'll easily convert the driver to it.
*/
struct da8xx_ddrctl_config_knob {
const char *name;
u32 reg;
u32 mask;
u32 shift;
};
static const struct da8xx_ddrctl_config_knob da8xx_ddrctl_knobs[] = {
{
.name = "da850-pbbpr",
.reg = 0x20,
.mask = 0xffffff00,
.shift = 0,
},
};
struct da8xx_ddrctl_setting {
const char *name;
u32 val;
};
struct da8xx_ddrctl_board_settings {
const char *board;
const struct da8xx_ddrctl_setting *settings;
};
static const struct da8xx_ddrctl_setting da850_lcdk_ddrctl_settings[] = {
{
.name = "da850-pbbpr",
.val = 0x20,
},
{ }
};
static const struct da8xx_ddrctl_board_settings da8xx_ddrctl_board_confs[] = {
{
.board = "ti,da850-lcdk",
.settings = da850_lcdk_ddrctl_settings,
},
};
static const struct da8xx_ddrctl_config_knob *
da8xx_ddrctl_match_knob(const struct da8xx_ddrctl_setting *setting)
{
const struct da8xx_ddrctl_config_knob *knob;
int i;
for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_knobs); i++) {
knob = &da8xx_ddrctl_knobs[i];
if (strcmp(knob->name, setting->name) == 0)
return knob;
}
return NULL;
}
static const struct da8xx_ddrctl_setting *da8xx_ddrctl_get_board_settings(void)
{
const struct da8xx_ddrctl_board_settings *board_settings;
int i;
for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_board_confs); i++) {
board_settings = &da8xx_ddrctl_board_confs[i];
if (of_machine_is_compatible(board_settings->board))
return board_settings->settings;
}
return NULL;
}
static int da8xx_ddrctl_probe(struct platform_device *pdev)
{
const struct da8xx_ddrctl_config_knob *knob;
const struct da8xx_ddrctl_setting *setting;
struct device_node *node;
struct resource *res;
void __iomem *ddrctl;
struct device *dev;
u32 reg;
dev = &pdev->dev;
node = dev->of_node;
setting = da8xx_ddrctl_get_board_settings();
if (!setting) {
dev_err(dev, "no settings defined for this board\n");
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ddrctl = devm_ioremap_resource(dev, res);
if (IS_ERR(ddrctl)) {
dev_err(dev, "unable to map memory controller registers\n");
return PTR_ERR(ddrctl);
}
for (; setting->name; setting++) {
knob = da8xx_ddrctl_match_knob(setting);
if (!knob) {
dev_warn(dev,
"no such config option: %s\n", setting->name);
continue;
}
if (knob->reg + sizeof(u32) > resource_size(res)) {
dev_warn(dev,
"register offset of '%s' exceeds mapped memory size\n",
knob->name);
continue;
}
reg = readl(ddrctl + knob->reg);
reg &= knob->mask;
reg |= setting->val << knob->shift;
dev_dbg(dev, "writing 0x%08x to %s\n", reg, setting->name);
writel(reg, ddrctl + knob->reg);
}
return 0;
}
static const struct of_device_id da8xx_ddrctl_of_match[] = {
{ .compatible = "ti,da850-ddr-controller", },
{ },
};
static struct platform_driver da8xx_ddrctl_driver = {
.probe = da8xx_ddrctl_probe,
.driver = {
.name = "da850-ddr-controller",
.of_match_table = da8xx_ddrctl_of_match,
},
};
module_platform_driver(da8xx_ddrctl_driver);
MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
MODULE_LICENSE("GPL v2");

42
drivers/misc/sram.c
View File

@ -19,12 +19,17 @@
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/list_sort.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <soc/at91/atmel-secumod.h>
#define SRAM_GRANULARITY 32
@ -334,12 +339,33 @@ static int sram_reserve_regions(struct sram_dev *sram, struct resource *res)
return ret;
}
static int atmel_securam_wait(void)
{
struct regmap *regmap;
u32 val;
regmap = syscon_regmap_lookup_by_compatible("atmel,sama5d2-secumod");
if (IS_ERR(regmap))
return -ENODEV;
return regmap_read_poll_timeout(regmap, AT91_SECUMOD_RAMRDY, val,
val & AT91_SECUMOD_RAMRDY_READY,
10000, 500000);
}
static const struct of_device_id sram_dt_ids[] = {
{ .compatible = "mmio-sram" },
{ .compatible = "atmel,sama5d2-securam", .data = atmel_securam_wait },
{}
};
static int sram_probe(struct platform_device *pdev)
{
struct sram_dev *sram;
struct resource *res;
size_t size;
int ret;
int (*init_func)(void);
sram = devm_kzalloc(&pdev->dev, sizeof(*sram), GFP_KERNEL);
if (!sram)
@ -384,6 +410,13 @@ static int sram_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, sram);
init_func = of_device_get_match_data(&pdev->dev);
if (init_func) {
ret = init_func();
if (ret)
return ret;
}
dev_dbg(sram->dev, "SRAM pool: %zu KiB @ 0x%p\n",
gen_pool_size(sram->pool) / 1024, sram->virt_base);
@ -405,17 +438,10 @@ static int sram_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id sram_dt_ids[] = {
{ .compatible = "mmio-sram" },
{}
};
#endif
static struct platform_driver sram_driver = {
.driver = {
.name = "sram",
.of_match_table = of_match_ptr(sram_dt_ids),
.of_match_table = sram_dt_ids,
},
.probe = sram_probe,
.remove = sram_remove,

1
drivers/reset/Kconfig
View File

@ -94,5 +94,6 @@ config RESET_ZYNQ
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"
endif

1
drivers/reset/Makefile
View File

@ -1,6 +1,7 @@
obj-y += core.o
obj-y += hisilicon/
obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o

43
drivers/reset/core.c
View File

@ -32,6 +32,9 @@ static LIST_HEAD(reset_controller_list);
* @refcnt: Number of gets of this reset_control
* @shared: Is this a shared (1), or an exclusive (0) reset_control?
* @deassert_cnt: Number of times this reset line has been deasserted
* @triggered_count: Number of times this reset line has been reset. Currently
* only used for shared resets, which means that the value
* will be either 0 or 1.
*/
struct reset_control {
struct reset_controller_dev *rcdev;
@ -40,6 +43,7 @@ struct reset_control {
unsigned int refcnt;
int shared;
atomic_t deassert_count;
atomic_t triggered_count;
};
/**
@ -134,18 +138,35 @@ EXPORT_SYMBOL_GPL(devm_reset_controller_register);
* reset_control_reset - reset the controlled device
* @rstc: reset controller
*
* Calling this on a shared reset controller is an error.
* On a shared reset line the actual reset pulse is only triggered once for the
* lifetime of the reset_control instance: for all but the first caller this is
* a no-op.
* Consumers must not use reset_control_(de)assert on shared reset lines when
* reset_control_reset has been used.
*/
int reset_control_reset(struct reset_control *rstc)
{
if (WARN_ON(IS_ERR_OR_NULL(rstc)) ||
WARN_ON(rstc->shared))
int ret;
if (WARN_ON(IS_ERR_OR_NULL(rstc)))
return -EINVAL;
if (rstc->rcdev->ops->reset)
return rstc->rcdev->ops->reset(rstc->rcdev, rstc->id);
if (!rstc->rcdev->ops->reset)
return -ENOTSUPP;
return -ENOTSUPP;
if (rstc->shared) {
if (WARN_ON(atomic_read(&rstc->deassert_count) != 0))
return -EINVAL;
if (atomic_inc_return(&rstc->triggered_count) != 1)
return 0;
}
ret = rstc->rcdev->ops->reset(rstc->rcdev, rstc->id);
if (rstc->shared && !ret)
atomic_dec(&rstc->triggered_count);
return ret;
}
EXPORT_SYMBOL_GPL(reset_control_reset);
@ -159,6 +180,8 @@ EXPORT_SYMBOL_GPL(reset_control_reset);
*
* For shared reset controls a driver cannot expect the hw's registers and
* internal state to be reset, but must be prepared for this to happen.
* Consumers must not use reset_control_reset on shared reset lines when
* reset_control_(de)assert has been used.
*/
int reset_control_assert(struct reset_control *rstc)
{
@ -169,6 +192,9 @@ int reset_control_assert(struct reset_control *rstc)
return -ENOTSUPP;
if (rstc->shared) {
if (WARN_ON(atomic_read(&rstc->triggered_count) != 0))
return -EINVAL;
if (WARN_ON(atomic_read(&rstc->deassert_count) == 0))
return -EINVAL;
@ -185,6 +211,8 @@ EXPORT_SYMBOL_GPL(reset_control_assert);
* @rstc: reset controller
*
* After calling this function, the reset is guaranteed to be deasserted.
* Consumers must not use reset_control_reset on shared reset lines when
* reset_control_(de)assert has been used.
*/
int reset_control_deassert(struct reset_control *rstc)
{
@ -195,6 +223,9 @@ int reset_control_deassert(struct reset_control *rstc)
return -ENOTSUPP;
if (rstc->shared) {
if (WARN_ON(atomic_read(&rstc->triggered_count) != 0))
return -EINVAL;
if (atomic_inc_return(&rstc->deassert_count) != 1)
return 0;
}

12
drivers/reset/reset-berlin.c
View File

@ -1,6 +1,8 @@
/*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Marvell Berlin reset driver
*
* Antoine Tenart <antoine.tenart@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
@ -12,7 +14,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
@ -91,7 +93,6 @@ static const struct of_device_id berlin_reset_dt_match[] = {
{ .compatible = "marvell,berlin2-reset" },
{ },
};
MODULE_DEVICE_TABLE(of, berlin_reset_dt_match);
static struct platform_driver berlin_reset_driver = {
.probe = berlin2_reset_probe,
@ -100,9 +101,4 @@ static struct platform_driver berlin_reset_driver = {
.of_match_table = berlin_reset_dt_match,
},
};
module_platform_driver(berlin_reset_driver);
MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
MODULE_DESCRIPTION("Marvell Berlin reset driver");
MODULE_LICENSE("GPL");
builtin_platform_driver(berlin_reset_driver);

32
drivers/reset/reset-lpc18xx.c
View File

@ -13,7 +13,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
@ -218,39 +218,17 @@ dis_clk_reg:
return ret;
}
static int lpc18xx_rgu_remove(struct platform_device *pdev)
{
struct lpc18xx_rgu_data *rc = platform_get_drvdata(pdev);
int ret;
ret = unregister_restart_handler(&rc->restart_nb);
if (ret)
dev_warn(&pdev->dev, "failed to unregister restart handler\n");
reset_controller_unregister(&rc->rcdev);
clk_disable_unprepare(rc->clk_delay);
clk_disable_unprepare(rc->clk_reg);
return 0;
}
static const struct of_device_id lpc18xx_rgu_match[] = {
{ .compatible = "nxp,lpc1850-rgu" },
{ }
};
MODULE_DEVICE_TABLE(of, lpc18xx_rgu_match);
static struct platform_driver lpc18xx_rgu_driver = {
.probe = lpc18xx_rgu_probe,
.remove = lpc18xx_rgu_remove,
.driver = {
.name = "lpc18xx-reset",
.of_match_table = lpc18xx_rgu_match,
.name = "lpc18xx-reset",
.of_match_table = lpc18xx_rgu_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(lpc18xx_rgu_driver);
MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
MODULE_DESCRIPTION("Reset driver for LPC18xx/43xx RGU");
MODULE_LICENSE("GPL v2");
builtin_platform_driver(lpc18xx_rgu_driver);

1
drivers/reset/reset-oxnas.c
View File

@ -80,6 +80,7 @@ static const struct reset_control_ops oxnas_reset_ops = {
static const struct of_device_id oxnas_reset_dt_ids[] = {
{ .compatible = "oxsemi,ox810se-reset", },
{ .compatible = "oxsemi,ox820-reset", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, oxnas_reset_dt_ids);

10
drivers/reset/reset-socfpga.c
View File

@ -1,4 +1,6 @@
/*
* Socfpga Reset Controller Driver
*
* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* based on
@ -16,7 +18,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
@ -148,8 +150,4 @@ static struct platform_driver socfpga_reset_driver = {
.of_match_table = socfpga_reset_dt_ids,
},
};
module_platform_driver(socfpga_reset_driver);
MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
MODULE_LICENSE("GPL");
builtin_platform_driver(socfpga_reset_driver);

9
drivers/reset/reset-sunxi.c
View File

@ -13,7 +13,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
@ -142,7 +142,6 @@ static const struct of_device_id sunxi_reset_dt_ids[] = {
{ .compatible = "allwinner,sun6i-a31-clock-reset", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
static int sunxi_reset_probe(struct platform_device *pdev)
{
@ -175,8 +174,4 @@ static struct platform_driver sunxi_reset_driver = {
.of_match_table = sunxi_reset_dt_ids,
},
};
module_platform_driver(sunxi_reset_driver);
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
MODULE_LICENSE("GPL");
builtin_platform_driver(sunxi_reset_driver);

10
drivers/reset/reset-zynq.c
View File

@ -3,6 +3,8 @@
*
* Xilinx Zynq Reset controller driver
*
* Author: Moritz Fischer <moritz.fischer@ettus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@ -15,7 +17,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@ -137,8 +139,4 @@ static struct platform_driver zynq_reset_driver = {
.of_match_table = zynq_reset_dt_ids,
},
};
module_platform_driver(zynq_reset_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
MODULE_DESCRIPTION("Zynq Reset Controller Driver");
builtin_platform_driver(zynq_reset_driver);

8
drivers/reset/sti/Kconfig
View File

@ -3,14 +3,6 @@ if ARCH_STI
config STI_RESET_SYSCFG
bool
config STIH415_RESET
bool
select STI_RESET_SYSCFG
config STIH416_RESET
bool
select STI_RESET_SYSCFG
config STIH407_RESET
bool
select STI_RESET_SYSCFG

2
drivers/reset/sti/Makefile
View File

@ -1,5 +1,3 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
obj-$(CONFIG_STIH407_RESET) += reset-stih407.o

112
drivers/reset/sti/reset-stih415.c
View File

@ -1,112 +0,0 @@
/*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited
* Author: Stephen Gallimore <stephen.gallimore@st.com>
* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <dt-bindings/reset/stih415-resets.h>
#include "reset-syscfg.h"
/*
* STiH415 Peripheral powerdown definitions.
*/
static const char stih415_front[] = "st,stih415-front-syscfg";
static const char stih415_rear[] = "st,stih415-rear-syscfg";
static const char stih415_sbc[] = "st,stih415-sbc-syscfg";
static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
#define STIH415_PDN_FRONT(_bit) \
_SYSCFG_RST_CH(stih415_front, SYSCFG_114, _bit, SYSSTAT_187, _bit)
#define STIH415_PDN_REAR(_cntl, _stat) \
_SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
#define STIH415_SRST_REAR(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih415_rear, _reg, _bit)
#define STIH415_SRST_SBC(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih415_sbc, _reg, _bit)
#define STIH415_SRST_FRONT(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih415_front, _reg, _bit)
#define STIH415_SRST_LPM(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih415_lpm, _reg, _bit)
#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
#define SYSCFG_376 0x130 /* Reset generator 0 control 0 */
#define SYSCFG_166 0x108 /* Softreset Ethernet 0 */
#define SYSCFG_31 0x7c /* Softreset Ethernet 1 */
#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
[STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
[STIH415_KEYSCAN_POWERDOWN] = STIH415_PDN_FRONT(2),
[STIH415_USB0_POWERDOWN] = STIH415_PDN_REAR(0, 0),
[STIH415_USB1_POWERDOWN] = STIH415_PDN_REAR(1, 1),
[STIH415_USB2_POWERDOWN] = STIH415_PDN_REAR(2, 2),
[STIH415_SATA0_POWERDOWN] = STIH415_PDN_REAR(3, 3),
[STIH415_SATA1_POWERDOWN] = STIH415_PDN_REAR(4, 4),
[STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
};
static const struct syscfg_reset_channel_data stih415_softresets[] = {
[STIH415_ETH0_SOFTRESET] = STIH415_SRST_FRONT(SYSCFG_166, 0),
[STIH415_ETH1_SOFTRESET] = STIH415_SRST_SBC(SYSCFG_31, 0),
[STIH415_IRB_SOFTRESET] = STIH415_SRST_LPM(LPM_SYSCFG_1, 6),
[STIH415_USB0_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 9),
[STIH415_USB1_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 10),
[STIH415_USB2_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 11),
[STIH415_KEYSCAN_SOFTRESET] = STIH415_SRST_LPM(LPM_SYSCFG_1, 8),
};
static struct syscfg_reset_controller_data stih415_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih415_powerdowns),
.channels = stih415_powerdowns,
};
static struct syscfg_reset_controller_data stih415_softreset_controller = {
.wait_for_ack = false,
.active_low = true,
.nr_channels = ARRAY_SIZE(stih415_softresets),
.channels = stih415_softresets,
};
static const struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
{ .compatible = "st,stih415-softreset",
.data = &stih415_softreset_controller, },
{},
};
static struct platform_driver stih415_reset_driver = {
.probe = syscfg_reset_probe,
.driver = {
.name = "reset-stih415",
.of_match_table = stih415_reset_match,
},
};
static int __init stih415_reset_init(void)
{
return platform_driver_register(&stih415_reset_driver);
}
arch_initcall(stih415_reset_init);

143
drivers/reset/sti/reset-stih416.c
View File

@ -1,143 +0,0 @@
/*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited
* Author: Stephen Gallimore <stephen.gallimore@st.com>
* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <dt-bindings/reset/stih416-resets.h>
#include "reset-syscfg.h"
/*
* STiH416 Peripheral powerdown definitions.
*/
static const char stih416_front[] = "st,stih416-front-syscfg";
static const char stih416_rear[] = "st,stih416-rear-syscfg";
static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
static const char stih416_cpu[] = "st,stih416-cpu-syscfg";
#define STIH416_PDN_FRONT(_bit) \
_SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
#define STIH416_PDN_REAR(_cntl, _stat) \
_SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
#define SYSCFG_2552 0x8A0 /* Reset Generator control 0 */
#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
#define SYSCFG_2553 0x8a4 /* Softreset SATA0/1, PCIE0/1 */
#define SYSCFG_7563 0x8cc /* MPE softresets 0 */
#define SYSCFG_7564 0x8d0 /* MPE softresets 1 */
#define STIH416_SRST_CPU(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih416_cpu, _reg, _bit)
#define STIH416_SRST_FRONT(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih416_front, _reg, _bit)
#define STIH416_SRST_REAR(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih416_rear, _reg, _bit)
#define STIH416_SRST_LPM(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih416_lpm, _reg, _bit)
#define STIH416_SRST_SBC(_reg, _bit) \
_SYSCFG_RST_CH_NO_ACK(stih416_sbc, _reg, _bit)
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
[STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
[STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
[STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
[STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
[STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
[STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
[STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
[STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
static const struct syscfg_reset_channel_data stih416_softresets[] = {
[STIH416_ETH0_SOFTRESET] = STIH416_SRST_FRONT(SYSCFG_1539, 0),
[STIH416_ETH1_SOFTRESET] = STIH416_SRST_SBC(SYSCFG_510, 0),
[STIH416_IRB_SOFTRESET] = STIH416_SRST_LPM(LPM_SYSCFG_1, 6),
[STIH416_USB0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 9),
[STIH416_USB1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 10),
[STIH416_USB2_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 11),
[STIH416_USB3_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 28),
[STIH416_SATA0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 7),
[STIH416_SATA1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 3),
[STIH416_PCIE0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 15),
[STIH416_PCIE1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 2),
[STIH416_AUD_DAC_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 14),
[STIH416_HDTVOUT_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 5),
[STIH416_VTAC_M_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 25),
[STIH416_VTAC_A_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 26),
[STIH416_SYNC_HD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 5),
[STIH416_SYNC_SD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 6),
[STIH416_BLITTER_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 10),
[STIH416_GPU_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 11),
[STIH416_VTAC_M_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 18),
[STIH416_VTAC_A_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 19),
[STIH416_VTG_AUX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 21),
[STIH416_JPEG_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 23),
[STIH416_HVA_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 2),
[STIH416_COMPO_M_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 3),
[STIH416_COMPO_A_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 4),
[STIH416_VP8_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 10),
[STIH416_VTG_MAIN_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 16),
[STIH416_KEYSCAN_SOFTRESET] = STIH416_SRST_LPM(LPM_SYSCFG_1, 8),
};
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
static struct syscfg_reset_controller_data stih416_softreset_controller = {
.wait_for_ack = false,
.active_low = true,
.nr_channels = ARRAY_SIZE(stih416_softresets),
.channels = stih416_softresets,
};
static const struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
{ .compatible = "st,stih416-softreset",
.data = &stih416_softreset_controller, },
{},
};
static struct platform_driver stih416_reset_driver = {
.probe = syscfg_reset_probe,
.driver = {
.name = "reset-stih416",
.of_match_table = stih416_reset_match,
},
};
static int __init stih416_reset_init(void)
{
return platform_driver_register(&stih416_reset_driver);
}
arch_initcall(stih416_reset_init);

2
drivers/reset/tegra/Kconfig Normal file
View File

@ -0,0 +1,2 @@
config RESET_TEGRA_BPMP
def_bool TEGRA_BPMP

1
drivers/reset/tegra/Makefile Normal file
View File

@ -0,0 +1 @@
obj-$(CONFIG_RESET_TEGRA_BPMP) += reset-bpmp.o

71
drivers/reset/tegra/reset-bpmp.c Normal file
View File

@ -0,0 +1,71 @@
/*
* Copyright (C) 2016 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/reset-controller.h>
#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>
static struct tegra_bpmp *to_tegra_bpmp(struct reset_controller_dev *rstc)
{
return container_of(rstc, struct tegra_bpmp, rstc);
}
static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,
enum mrq_reset_commands command,
unsigned int id)
{
struct tegra_bpmp *bpmp = to_tegra_bpmp(rstc);
struct mrq_reset_request request;
struct tegra_bpmp_message msg;
memset(&request, 0, sizeof(request));
request.cmd = command;
request.reset_id = id;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_RESET;
msg.tx.data = &request;
msg.tx.size = sizeof(request);
return tegra_bpmp_transfer(bpmp, &msg);
}
static int tegra_bpmp_reset_module(struct reset_controller_dev *rstc,
unsigned long id)
{
return tegra_bpmp_reset_common(rstc, CMD_RESET_MODULE, id);
}
static int tegra_bpmp_reset_assert(struct reset_controller_dev *rstc,
unsigned long id)
{
return tegra_bpmp_reset_common(rstc, CMD_RESET_ASSERT, id);
}
static int tegra_bpmp_reset_deassert(struct reset_controller_dev *rstc,
unsigned long id)
{
return tegra_bpmp_reset_common(rstc, CMD_RESET_DEASSERT, id);
}
static const struct reset_control_ops tegra_bpmp_reset_ops = {
.reset = tegra_bpmp_reset_module,
.assert = tegra_bpmp_reset_assert,
.deassert = tegra_bpmp_reset_deassert,
};
int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp)
{
bpmp->rstc.ops = &tegra_bpmp_reset_ops;
bpmp->rstc.owner = THIS_MODULE;
bpmp->rstc.of_node = bpmp->dev->of_node;
bpmp->rstc.nr_resets = bpmp->soc->num_resets;
return devm_reset_controller_register(bpmp->dev, &bpmp->rstc);
}

2
drivers/soc/mediatek/Kconfig
View File

@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM

467
drivers/soc/mediatek/mtk-scpsys.c
View File

@ -11,17 +11,16 @@
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/infracfg.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt8173-power.h>
#define SPM_VDE_PWR_CON 0x0210
@ -29,11 +28,17 @@
#define SPM_VEN_PWR_CON 0x0230
#define SPM_ISP_PWR_CON 0x0238
#define SPM_DIS_PWR_CON 0x023c
#define SPM_CONN_PWR_CON 0x0280
#define SPM_VEN2_PWR_CON 0x0298
#define SPM_AUDIO_PWR_CON 0x029c
#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
#define SPM_ETH_PWR_CON 0x02a0
#define SPM_HIF_PWR_CON 0x02a4
#define SPM_IFR_MSC_PWR_CON 0x02a8
#define SPM_MFG_2D_PWR_CON 0x02c0
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
#define SPM_USB_PWR_CON 0x02cc
#define SPM_PWR_STATUS 0x060c
#define SPM_PWR_STATUS_2ND 0x0610
@ -43,10 +48,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
#define PWR_STATUS_MFG BIT(4)
#define PWR_STATUS_ISP BIT(5)
#define PWR_STATUS_VDEC BIT(7)
#define PWR_STATUS_BDP BIT(14)
#define PWR_STATUS_ETH BIT(15)
#define PWR_STATUS_HIF BIT(16)
#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_VENC_LT BIT(20)
#define PWR_STATUS_VENC BIT(21)
#define PWR_STATUS_MFG_2D BIT(22)
@ -55,12 +65,23 @@
#define PWR_STATUS_USB BIT(25)
enum clk_id {
MT8173_CLK_NONE,
MT8173_CLK_MM,
MT8173_CLK_MFG,
MT8173_CLK_VENC,
MT8173_CLK_VENC_LT,
MT8173_CLK_MAX,
CLK_NONE,
CLK_MM,
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
CLK_ETHIF,
CLK_MAX,
};
static const char * const clk_names[] = {
NULL,
"mm",
"mfg",
"venc",
"venc_lt",
"ethif",
NULL,
};
#define MAX_CLKS 2
@ -76,98 +97,6 @@ struct scp_domain_data {
bool active_wakeup;
};
static const struct scp_domain_data scp_domain_data[] = {
[MT8173_POWER_DOMAIN_VDEC] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {MT8173_CLK_MM},
},
[MT8173_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = PWR_STATUS_VENC,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
},
[MT8173_POWER_DOMAIN_ISP] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = {MT8173_CLK_MM},
},
[MT8173_POWER_DOMAIN_MM] = {
.name = "mm",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {MT8173_CLK_MM},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1,
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
.name = "venc_lt",
.sta_mask = PWR_STATUS_VENC_LT,
.ctl_offs = SPM_VEN2_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
},
[MT8173_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = PWR_STATUS_AUDIO,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {MT8173_CLK_NONE},
},
[MT8173_POWER_DOMAIN_USB] = {
.name = "usb",
.sta_mask = PWR_STATUS_USB,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {MT8173_CLK_NONE},
.active_wakeup = true,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
.sta_mask = PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
.clk_id = {MT8173_CLK_MFG},
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
.sta_mask = PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = {MT8173_CLK_NONE},
},
[MT8173_POWER_DOMAIN_MFG] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
.clk_id = {MT8173_CLK_NONE},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
},
};
#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
struct scp;
struct scp_domain {
@ -179,7 +108,7 @@ struct scp_domain {
};
struct scp {
struct scp_domain domains[NUM_DOMAINS];
struct scp_domain *domains;
struct genpd_onecell_data pd_data;
struct device *dev;
void __iomem *base;
@ -408,57 +337,55 @@ static bool scpsys_active_wakeup(struct device *dev)
return scpd->data->active_wakeup;
}
static int scpsys_probe(struct platform_device *pdev)
static void init_clks(struct platform_device *pdev, struct clk **clk)
{
int i;
for (i = CLK_NONE + 1; i < CLK_MAX; i++)
clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
}
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
int i, j, ret;
int i, j;
struct scp *scp;
struct clk *clk[MT8173_CLK_MAX];
struct clk *clk[CLK_MAX];
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
if (!scp)
return -ENOMEM;
return ERR_PTR(-ENOMEM);
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
scp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(scp->base))
return PTR_ERR(scp->base);
return ERR_CAST(scp->base);
scp->domains = devm_kzalloc(&pdev->dev,
sizeof(*scp->domains) * num, GFP_KERNEL);
if (!scp->domains)
return ERR_PTR(-ENOMEM);
pd_data = &scp->pd_data;
pd_data->domains = devm_kzalloc(&pdev->dev,
sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
sizeof(*pd_data->domains) * num, GFP_KERNEL);
if (!pd_data->domains)
return -ENOMEM;
clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
if (IS_ERR(clk[MT8173_CLK_MM]))
return PTR_ERR(clk[MT8173_CLK_MM]);
clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
if (IS_ERR(clk[MT8173_CLK_MFG]))
return PTR_ERR(clk[MT8173_CLK_MFG]);
clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
if (IS_ERR(clk[MT8173_CLK_VENC]))
return PTR_ERR(clk[MT8173_CLK_VENC]);
clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
return ERR_PTR(-ENOMEM);
scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"infracfg");
if (IS_ERR(scp->infracfg)) {
dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
PTR_ERR(scp->infracfg));
return PTR_ERR(scp->infracfg);
return ERR_CAST(scp->infracfg);
}
for (i = 0; i < NUM_DOMAINS; i++) {
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
@ -467,13 +394,15 @@ static int scpsys_probe(struct platform_device *pdev)
if (PTR_ERR(scpd->supply) == -ENODEV)
scpd->supply = NULL;
else
return PTR_ERR(scpd->supply);
return ERR_CAST(scpd->supply);
}
}
pd_data->num_domains = NUM_DOMAINS;
pd_data->num_domains = num;
for (i = 0; i < NUM_DOMAINS; i++) {
init_clks(pdev, clk);
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
const struct scp_domain_data *data = &scp_domain_data[i];
@ -482,13 +411,37 @@ static int scpsys_probe(struct platform_device *pdev)
scpd->scp = scp;
scpd->data = data;
for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
scpd->clk[j] = clk[data->clk_id[j]];
for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
struct clk *c = clk[data->clk_id[j]];
if (IS_ERR(c)) {
dev_err(&pdev->dev, "%s: clk unavailable\n",
data->name);
return ERR_CAST(c);
}
scpd->clk[j] = c;
}
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
}
return scp;
}
static void mtk_register_power_domains(struct platform_device *pdev,
struct scp *scp, int num)
{
struct genpd_onecell_data *pd_data;
int i, ret;
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
/*
* Initially turn on all domains to make the domains usable
@ -507,6 +460,222 @@ static int scpsys_probe(struct platform_device *pdev)
* valid.
*/
pd_data = &scp->pd_data;
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
if (ret)
dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
}
/*
* MT2701 power domain support
*/
static const struct scp_domain_data scp_domain_data_mt2701[] = {
[MT2701_POWER_DOMAIN_CONN] = {
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
.bus_prot_mask = 0x0104,
.clk_id = {CLK_NONE},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_DISP] = {
.name = "disp",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.clk_id = {CLK_MM},
.bus_prot_mask = 0x0002,
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_MFG] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {CLK_MFG},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_VDEC] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {CLK_MM},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_ISP] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = {CLK_MM},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_BDP] = {
.name = "bdp",
.sta_mask = PWR_STATUS_BDP,
.ctl_offs = SPM_BDP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.clk_id = {CLK_NONE},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_ETH] = {
.name = "eth",
.sta_mask = PWR_STATUS_ETH,
.ctl_offs = SPM_ETH_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_ETHIF},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_HIF] = {
.name = "hif",
.sta_mask = PWR_STATUS_HIF,
.ctl_offs = SPM_HIF_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_ETHIF},
.active_wakeup = true,
},
[MT2701_POWER_DOMAIN_IFR_MSC] = {
.name = "ifr_msc",
.sta_mask = PWR_STATUS_IFR_MSC,
.ctl_offs = SPM_IFR_MSC_PWR_CON,
.clk_id = {CLK_NONE},
.active_wakeup = true,
},
};
#define NUM_DOMAINS_MT2701 ARRAY_SIZE(scp_domain_data_mt2701)
static int __init scpsys_probe_mt2701(struct platform_device *pdev)
{
struct scp *scp;
scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
if (IS_ERR(scp))
return PTR_ERR(scp);
mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
return 0;
}
/*
* MT8173 power domain support
*/
static const struct scp_domain_data scp_domain_data_mt8173[] = {
[MT8173_POWER_DOMAIN_VDEC] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {CLK_MM},
},
[MT8173_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = PWR_STATUS_VENC,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_MM, CLK_VENC},
},
[MT8173_POWER_DOMAIN_ISP] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = {CLK_MM},
},
[MT8173_POWER_DOMAIN_MM] = {
.name = "mm",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = {CLK_MM},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1,
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
.name = "venc_lt",
.sta_mask = PWR_STATUS_VENC_LT,
.ctl_offs = SPM_VEN2_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_MM, CLK_VENC_LT},
},
[MT8173_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = PWR_STATUS_AUDIO,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_USB] = {
.name = "usb",
.sta_mask = PWR_STATUS_USB,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = {CLK_NONE},
.active_wakeup = true,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
.sta_mask = PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
.clk_id = {CLK_MFG},
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
.sta_mask = PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_MFG] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
.clk_id = {CLK_NONE},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
},
};
#define NUM_DOMAINS_MT8173 ARRAY_SIZE(scp_domain_data_mt8173)
static int __init scpsys_probe_mt8173(struct platform_device *pdev)
{
struct scp *scp;
struct genpd_onecell_data *pd_data;
int ret;
scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
if (IS_ERR(scp))
return PTR_ERR(scp);
mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);
pd_data = &scp->pd_data;
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
if (ret && IS_ENABLED(CONFIG_PM))
@ -517,21 +686,39 @@ static int scpsys_probe(struct platform_device *pdev)
if (ret && IS_ENABLED(CONFIG_PM))
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
if (ret)
dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
return 0;
}
/*
* scpsys driver init
*/
static const struct of_device_id of_scpsys_match_tbl[] = {
{
.compatible = "mediatek,mt2701-scpsys",
.data = scpsys_probe_mt2701,
}, {
.compatible = "mediatek,mt8173-scpsys",
.data = scpsys_probe_mt8173,
}, {
/* sentinel */
}
};
static int scpsys_probe(struct platform_device *pdev)
{
int (*probe)(struct platform_device *);
const struct of_device_id *of_id;
of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
if (!of_id || !of_id->data)
return -EINVAL;
probe = of_id->data;
return probe(pdev);
}
static struct platform_driver scpsys_drv = {
.probe = scpsys_probe,
.driver = {

4
drivers/soc/renesas/Makefile
View File

@ -1,8 +1,12 @@
obj-$(CONFIG_SOC_BUS) += renesas-soc.o
obj-$(CONFIG_ARCH_RCAR_GEN1) += rcar-rst.o
obj-$(CONFIG_ARCH_RCAR_GEN2) += rcar-rst.o
obj-$(CONFIG_ARCH_R8A7795) += rcar-rst.o
obj-$(CONFIG_ARCH_R8A7796) += rcar-rst.o
obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o
obj-$(CONFIG_ARCH_R8A7745) += rcar-sysc.o r8a7745-sysc.o
obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o

32
drivers/soc/renesas/r8a7743-sysc.c Normal file
View File

@ -0,0 +1,32 @@
/*
* Renesas RZ/G1M System Controller
*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation; of the License.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7743-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7743_areas[] __initconst = {
{ "always-on", 0, 0, R8A7743_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca15-scu", 0x180, 0, R8A7743_PD_CA15_SCU, R8A7743_PD_ALWAYS_ON,
PD_SCU },
{ "ca15-cpu0", 0x40, 0, R8A7743_PD_CA15_CPU0, R8A7743_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu1", 0x40, 1, R8A7743_PD_CA15_CPU1, R8A7743_PD_CA15_SCU,
PD_CPU_NOCR },
{ "sgx", 0xc0, 0, R8A7743_PD_SGX, R8A7743_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7743_sysc_info __initconst = {
.areas = r8a7743_areas,
.num_areas = ARRAY_SIZE(r8a7743_areas),
};

32
drivers/soc/renesas/r8a7745-sysc.c Normal file
View File

@ -0,0 +1,32 @@
/*
* Renesas RZ/G1E System Controller
*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation; of the License.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7745-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7745_areas[] __initconst = {
{ "always-on", 0, 0, R8A7745_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca7-scu", 0x100, 0, R8A7745_PD_CA7_SCU, R8A7745_PD_ALWAYS_ON,
PD_SCU },
{ "ca7-cpu0", 0x1c0, 0, R8A7745_PD_CA7_CPU0, R8A7745_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu1", 0x1c0, 1, R8A7745_PD_CA7_CPU1, R8A7745_PD_CA7_SCU,
PD_CPU_NOCR },
{ "sgx", 0xc0, 0, R8A7745_PD_SGX, R8A7745_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7745_sysc_info __initconst = {
.areas = r8a7745_areas,
.num_areas = ARRAY_SIZE(r8a7745_areas),
};

6
drivers/soc/renesas/rcar-sysc.c
View File

@ -275,6 +275,12 @@ finalize:
}
static const struct of_device_id rcar_sysc_matches[] = {
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
#endif
#ifdef CONFIG_ARCH_R8A7779
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
#endif

2
drivers/soc/renesas/rcar-sysc.h
View File

@ -50,6 +50,8 @@ struct rcar_sysc_info {
unsigned int num_areas;
};
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;

257
drivers/soc/renesas/renesas-soc.c Normal file
View File

@ -0,0 +1,257 @@
/*
* Renesas SoC Identification
*
* Copyright (C) 2014-2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sys_soc.h>
struct renesas_family {
const char name[16];
u32 reg; /* CCCR or PRR, if not in DT */
};
static const struct renesas_family fam_rcar_gen1 __initconst __maybe_unused = {
.name = "R-Car Gen1",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rcar_gen2 __initconst __maybe_unused = {
.name = "R-Car Gen2",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = {
.name = "R-Car Gen3",
.reg = 0xfff00044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
.name = "R-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
};
static const struct renesas_family fam_rza __initconst __maybe_unused = {
.name = "RZ/A",
};
static const struct renesas_family fam_rzg __initconst __maybe_unused = {
.name = "RZ/G",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
};
struct renesas_soc {
const struct renesas_family *family;
u8 id;
};
static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = {
.family = &fam_rza,
};
static const struct renesas_soc soc_rmobile_ape6 __initconst __maybe_unused = {
.family = &fam_rmobile,
.id = 0x3f,
};
static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = {
.family = &fam_rmobile,
.id = 0x40,
};
static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x47,
};
static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.family = &fam_rzg,
.id = 0x4c,
};
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
static const struct renesas_soc soc_rcar_h1 __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
.id = 0x3b,
};
static const struct renesas_soc soc_rcar_h2 __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x45,
};
static const struct renesas_soc soc_rcar_m2_w __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x47,
};
static const struct renesas_soc soc_rcar_v2h __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4a,
};
static const struct renesas_soc soc_rcar_m2_n __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4b,
};
static const struct renesas_soc soc_rcar_e2 __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4c,
};
static const struct renesas_soc soc_rcar_h3 __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x4f,
};
static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x52,
};
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
.family = &fam_shmobile,
.id = 0x37,
};
static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R7S72100
{ .compatible = "renesas,r7s72100", .data = &soc_rz_a1h },
#endif
#ifdef CONFIG_ARCH_R8A73A4
{ .compatible = "renesas,r8a73a4", .data = &soc_rmobile_ape6 },
#endif
#ifdef CONFIG_ARCH_R8A7740
{ .compatible = "renesas,r8a7740", .data = &soc_rmobile_a1 },
#endif
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
#endif
#ifdef CONFIG_ARCH_R8A7778
{ .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
#endif
#ifdef CONFIG_ARCH_R8A7779
{ .compatible = "renesas,r8a7779", .data = &soc_rcar_h1 },
#endif
#ifdef CONFIG_ARCH_R8A7790
{ .compatible = "renesas,r8a7790", .data = &soc_rcar_h2 },
#endif
#ifdef CONFIG_ARCH_R8A7791
{ .compatible = "renesas,r8a7791", .data = &soc_rcar_m2_w },
#endif
#ifdef CONFIG_ARCH_R8A7792
{ .compatible = "renesas,r8a7792", .data = &soc_rcar_v2h },
#endif
#ifdef CONFIG_ARCH_R8A7793
{ .compatible = "renesas,r8a7793", .data = &soc_rcar_m2_n },
#endif
#ifdef CONFIG_ARCH_R8A7794
{ .compatible = "renesas,r8a7794", .data = &soc_rcar_e2 },
#endif
#ifdef CONFIG_ARCH_R8A7795
{ .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
#endif
#ifdef CONFIG_ARCH_R8A7796
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
{ /* sentinel */ }
};
static int __init renesas_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
const struct renesas_family *family;
const struct of_device_id *match;
const struct renesas_soc *soc;
void __iomem *chipid = NULL;
struct soc_device *soc_dev;
struct device_node *np;
unsigned int product;
match = of_match_node(renesas_socs, of_root);
if (!match)
return -ENODEV;
soc = match->data;
family = soc->family;
/* Try PRR first, then hardcoded fallback */
np = of_find_compatible_node(NULL, NULL, "renesas,prr");
if (np) {
chipid = of_iomap(np, 0);
of_node_put(np);
} else if (soc->id) {
chipid = ioremap(family->reg, 4);
}
if (chipid) {
product = readl(chipid);
iounmap(chipid);
if (soc->id && ((product >> 8) & 0xff) != soc->id) {
pr_warn("SoC mismatch (product = 0x%x)\n", product);
return -ENODEV;
}
}
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
np = of_find_node_by_path("/");
of_property_read_string(np, "model", &soc_dev_attr->machine);
of_node_put(np);
soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
GFP_KERNEL);
if (chipid)
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
((product >> 4) & 0x0f) + 1,
product & 0xf);
pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree_const(soc_dev_attr->soc_id);
kfree_const(soc_dev_attr->family);
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
}
return 0;
}
core_initcall(renesas_soc_init);

81
drivers/soc/rockchip/pm_domains.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/err.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
@ -105,12 +106,24 @@ static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
return (val & pd_info->idle_mask) == pd_info->idle_mask;
}
static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
{
unsigned int val;
regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
return val;
}
static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
bool idle)
{
const struct rockchip_domain_info *pd_info = pd->info;
struct generic_pm_domain *genpd = &pd->genpd;
struct rockchip_pmu *pmu = pd->pmu;
unsigned int target_ack;
unsigned int val;
bool is_idle;
int ret;
if (pd_info->req_mask == 0)
return 0;
@ -120,12 +133,26 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
dsb(sy);
do {
regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
} while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
/* Wait util idle_ack = 1 */
target_ack = idle ? pd_info->ack_mask : 0;
ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
(val & pd_info->ack_mask) == target_ack,
0, 10000);
if (ret) {
dev_err(pmu->dev,
"failed to get ack on domain '%s', val=0x%x\n",
genpd->name, val);
return ret;
}
while (rockchip_pmu_domain_is_idle(pd) != idle)
cpu_relax();
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
is_idle, is_idle == idle, 0, 10000);
if (ret) {
dev_err(pmu->dev,
"failed to set idle on domain '%s', val=%d\n",
genpd->name, is_idle);
return ret;
}
return 0;
}
@ -198,6 +225,8 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
bool on)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
bool is_on;
if (pd->info->pwr_mask == 0)
return;
@ -207,8 +236,13 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
dsb(sy);
while (rockchip_pmu_domain_is_on(pd) != on)
cpu_relax();
if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000)) {
dev_err(pmu->dev,
"failed to set domain '%s', val=%d\n",
genpd->name, is_on);
return;
}
}
static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
@ -445,7 +479,16 @@ err_out:
static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
{
int i;
int i, ret;
/*
* We're in the error cleanup already, so we only complain,
* but won't emit another error on top of the original one.
*/
ret = pm_genpd_remove(&pd->genpd);
if (ret < 0)
dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
pd->genpd.name, ret);
for (i = 0; i < pd->num_clks; i++) {
clk_unprepare(pd->clks[i]);
@ -597,10 +640,12 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
* Configure power up and down transition delays for CORE
* and GPU domains.
*/
rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
pmu_info->core_power_transition_time);
rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
pmu_info->gpu_power_transition_time);
if (pmu_info->core_power_transition_time)
rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
pmu_info->core_power_transition_time);
if (pmu_info->gpu_pwrcnt_offset)
rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
pmu_info->gpu_power_transition_time);
error = -ENODEV;
@ -627,7 +672,11 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
goto err_out;
}
of_genpd_add_provider_onecell(np, &pmu->genpd_data);
error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
if (error) {
dev_err(dev, "failed to add provider: %d\n", error);
goto err_out;
}
return 0;
@ -722,11 +771,7 @@ static const struct rockchip_pmu_info rk3399_pmu = {
.idle_offset = 0x64,
.ack_offset = 0x68,
.core_pwrcnt_offset = 0x9c,
.gpu_pwrcnt_offset = 0xa4,
.core_power_transition_time = 24,
.gpu_power_transition_time = 24,
/* ARM Trusted Firmware manages power transition times */
.num_domains = ARRAY_SIZE(rk3399_pm_domains),
.domain_info = rk3399_pm_domains,

14
drivers/soc/tegra/Kconfig
View File

@ -77,5 +77,19 @@ config ARCH_TEGRA_210_SOC
controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
config ARCH_TEGRA_186_SOC
bool "NVIDIA Tegra186 SoC"
select MAILBOX
select TEGRA_BPMP
select TEGRA_HSP_MBOX
select TEGRA_IVC
help
Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
combination of Denver and Cortex-A57 CPU cores and a GPU based on
the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
used for audio processing, hardware video encoders/decoders with
multi-format support, ISP for image capture processing and BPMP for
power management.
endif
endif

426
drivers/soc/tegra/pmc.c
View File

@ -45,29 +45,31 @@
#include <soc/tegra/pmc.h>
#define PMC_CNTRL 0x0
#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
#define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
#define PMC_CNTRL_MAIN_RST (1 << 4)
#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
#define PMC_CNTRL_MAIN_RST BIT(4)
#define DPD_SAMPLE 0x020
#define DPD_SAMPLE_ENABLE (1 << 0)
#define DPD_SAMPLE_ENABLE BIT(0)
#define DPD_SAMPLE_DISABLE (0 << 0)
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
#define PWRGATE_TOGGLE_START BIT(8)
#define REMOVE_CLAMPING 0x34
#define PWRGATE_STATUS 0x38
#define PMC_PWR_DET 0x48
#define PMC_SCRATCH0 0x50
#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
#define PMC_SCRATCH0_MODE_RCM (1 << 1)
#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
#define PMC_SCRATCH0_MODE_RCM BIT(1)
#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
PMC_SCRATCH0_MODE_BOOTLOADER | \
PMC_SCRATCH0_MODE_RCM)
@ -75,11 +77,13 @@
#define PMC_CPUPWRGOOD_TIMER 0xc8
#define PMC_CPUPWROFF_TIMER 0xcc
#define PMC_PWR_DET_VALUE 0xe4
#define PMC_SCRATCH41 0x140
#define PMC_SENSOR_CTRL 0x1b0
#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
#define PMC_RST_STATUS 0x1b4
#define PMC_RST_STATUS_POR 0
@ -90,10 +94,10 @@
#define PMC_RST_STATUS_AOTAG 5
#define IO_DPD_REQ 0x1b8
#define IO_DPD_REQ_CODE_IDLE (0 << 30)
#define IO_DPD_REQ_CODE_OFF (1 << 30)
#define IO_DPD_REQ_CODE_ON (2 << 30)
#define IO_DPD_REQ_CODE_MASK (3 << 30)
#define IO_DPD_REQ_CODE_IDLE (0U << 30)
#define IO_DPD_REQ_CODE_OFF (1U << 30)
#define IO_DPD_REQ_CODE_ON (2U << 30)
#define IO_DPD_REQ_CODE_MASK (3U << 30)
#define IO_DPD_STATUS 0x1bc
#define IO_DPD2_REQ 0x1c0
@ -101,16 +105,16 @@
#define SEL_DPD_TIM 0x1c8
#define PMC_SCRATCH54 0x258
#define PMC_SCRATCH54_DATA_SHIFT 8
#define PMC_SCRATCH54_ADDR_SHIFT 0
#define PMC_SCRATCH54_DATA_SHIFT 8
#define PMC_SCRATCH54_ADDR_SHIFT 0
#define PMC_SCRATCH55 0x25c
#define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
#define PMC_SCRATCH55_PINMUX_SHIFT 24
#define PMC_SCRATCH55_16BITOP (1 << 15)
#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
#define PMC_SCRATCH55_PINMUX_SHIFT 24
#define PMC_SCRATCH55_16BITOP BIT(15)
#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
#define GPU_RG_CNTRL 0x2d4
@ -124,6 +128,12 @@ struct tegra_powergate {
unsigned int num_resets;
};
struct tegra_io_pad_soc {
enum tegra_io_pad id;
unsigned int dpd;
unsigned int voltage;
};
struct tegra_pmc_soc {
unsigned int num_powergates;
const char *const *powergates;
@ -132,6 +142,9 @@ struct tegra_pmc_soc {
bool has_tsense_reset;
bool has_gpu_clamps;
const struct tegra_io_pad_soc *io_pads;
unsigned int num_io_pads;
};
/**
@ -238,8 +251,6 @@ static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
return i;
}
dev_err(pmc->dev, "powergate %s not found\n", name);
return -ENODEV;
}
@ -456,13 +467,12 @@ disable_clks:
static int tegra_genpd_power_on(struct generic_pm_domain *domain)
{
struct tegra_powergate *pg = to_powergate(domain);
struct tegra_pmc *pmc = pg->pmc;
int err;
err = tegra_powergate_power_up(pg, true);
if (err)
dev_err(pmc->dev, "failed to turn on PM domain %s: %d\n",
pg->genpd.name, err);
pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
err);
return err;
}
@ -470,13 +480,12 @@ static int tegra_genpd_power_on(struct generic_pm_domain *domain)
static int tegra_genpd_power_off(struct generic_pm_domain *domain)
{
struct tegra_powergate *pg = to_powergate(domain);
struct tegra_pmc *pmc = pg->pmc;
int err;
err = tegra_powergate_power_down(pg);
if (err)
dev_err(pmc->dev, "failed to turn off PM domain %s: %d\n",
pg->genpd.name, err);
pr_err("failed to turn off PM domain %s: %d\n",
pg->genpd.name, err);
return err;
}
@ -801,8 +810,7 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
id = tegra_powergate_lookup(pmc, np->name);
if (id < 0) {
dev_err(pmc->dev, "powergate lookup failed for %s: %d\n",
np->name, id);
pr_err("powergate lookup failed for %s: %d\n", np->name, id);
goto free_mem;
}
@ -822,20 +830,22 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
err = tegra_powergate_of_get_clks(pg, np);
if (err < 0) {
dev_err(pmc->dev, "failed to get clocks for %s: %d\n",
np->name, err);
pr_err("failed to get clocks for %s: %d\n", np->name, err);
goto set_available;
}
err = tegra_powergate_of_get_resets(pg, np, off);
if (err < 0) {
dev_err(pmc->dev, "failed to get resets for %s: %d\n",
np->name, err);
pr_err("failed to get resets for %s: %d\n", np->name, err);
goto remove_clks;
}
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
goto power_on_cleanup;
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
if (off)
WARN_ON(tegra_powergate_power_up(pg, true));
goto remove_resets;
}
/*
* FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
@ -846,25 +856,33 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
* to be unused.
*/
if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
(id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC))
goto power_on_cleanup;
(id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
if (off)
WARN_ON(tegra_powergate_power_up(pg, true));
pm_genpd_init(&pg->genpd, NULL, off);
err = of_genpd_add_provider_simple(np, &pg->genpd);
if (err < 0) {
dev_err(pmc->dev, "failed to add genpd provider for %s: %d\n",
np->name, err);
goto remove_resets;
}
dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name);
err = pm_genpd_init(&pg->genpd, NULL, off);
if (err < 0) {
pr_err("failed to initialise PM domain %s: %d\n", np->name,
err);
goto remove_resets;
}
err = of_genpd_add_provider_simple(np, &pg->genpd);
if (err < 0) {
pr_err("failed to add PM domain provider for %s: %d\n",
np->name, err);
goto remove_genpd;
}
pr_debug("added PM domain %s\n", pg->genpd.name);
return;
power_on_cleanup:
if (off)
WARN_ON(tegra_powergate_power_up(pg, true));
remove_genpd:
pm_genpd_remove(&pg->genpd);
remove_resets:
while (pg->num_resets--)
@ -908,21 +926,36 @@ static void tegra_powergate_init(struct tegra_pmc *pmc,
of_node_put(np);
}
static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
unsigned long *status, unsigned int *bit)
static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
{
unsigned int i;
for (i = 0; i < pmc->soc->num_io_pads; i++)
if (pmc->soc->io_pads[i].id == id)
return &pmc->soc->io_pads[i];
return NULL;
}
static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
unsigned long *status, u32 *mask)
{
const struct tegra_io_pad_soc *pad;
unsigned long rate, value;
*bit = id % 32;
pad = tegra_io_pad_find(pmc, id);
if (!pad) {
pr_err("invalid I/O pad ID %u\n", id);
return -ENOENT;
}
/*
* There are two sets of 30 bits to select IO rails, but bits 30 and
* 31 are control bits rather than IO rail selection bits.
*/
if (id > 63 || *bit == 30 || *bit == 31)
return -EINVAL;
if (pad->dpd == UINT_MAX)
return -ENOTSUPP;
if (id < 32) {
*mask = BIT(pad->dpd % 32);
if (pad->dpd < 32) {
*status = IO_DPD_STATUS;
*request = IO_DPD_REQ;
} else {
@ -931,6 +964,10 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
}
rate = clk_get_rate(pmc->clk);
if (!rate) {
pr_err("failed to get clock rate\n");
return -ENODEV;
}
tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
@ -942,10 +979,10 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
return 0;
}
static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
unsigned long val, unsigned long timeout)
static int tegra_io_pad_poll(unsigned long offset, u32 mask,
u32 val, unsigned long timeout)
{
unsigned long value;
u32 value;
timeout = jiffies + msecs_to_jiffies(timeout);
@ -960,66 +997,163 @@ static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
return -ETIMEDOUT;
}
static void tegra_io_rail_unprepare(void)
static void tegra_io_pad_unprepare(void)
{
tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
}
int tegra_io_rail_power_on(unsigned int id)
/**
* tegra_io_pad_power_enable() - enable power to I/O pad
* @id: Tegra I/O pad ID for which to enable power
*
* Returns: 0 on success or a negative error code on failure.
*/
int tegra_io_pad_power_enable(enum tegra_io_pad id)
{
unsigned long request, status;
unsigned int bit;
u32 mask;
int err;
mutex_lock(&pmc->powergates_lock);
err = tegra_io_rail_prepare(id, &request, &status, &bit);
if (err)
goto error;
tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | BIT(bit), request);
err = tegra_io_rail_poll(status, BIT(bit), 0, 250);
if (err) {
pr_info("tegra_io_rail_poll() failed: %d\n", err);
goto error;
err = tegra_io_pad_prepare(id, &request, &status, &mask);
if (err < 0) {
pr_err("failed to prepare I/O pad: %d\n", err);
goto unlock;
}
tegra_io_rail_unprepare();
tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
err = tegra_io_pad_poll(status, mask, 0, 250);
if (err < 0) {
pr_err("failed to enable I/O pad: %d\n", err);
goto unlock;
}
tegra_io_pad_unprepare();
unlock:
mutex_unlock(&pmc->powergates_lock);
return err;
}
EXPORT_SYMBOL(tegra_io_pad_power_enable);
/**
* tegra_io_pad_power_disable() - disable power to I/O pad
* @id: Tegra I/O pad ID for which to disable power
*
* Returns: 0 on success or a negative error code on failure.
*/
int tegra_io_pad_power_disable(enum tegra_io_pad id)
{
unsigned long request, status;
u32 mask;
int err;
mutex_lock(&pmc->powergates_lock);
err = tegra_io_pad_prepare(id, &request, &status, &mask);
if (err < 0) {
pr_err("failed to prepare I/O pad: %d\n", err);
goto unlock;
}
tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
err = tegra_io_pad_poll(status, mask, mask, 250);
if (err < 0) {
pr_err("failed to disable I/O pad: %d\n", err);
goto unlock;
}
tegra_io_pad_unprepare();
unlock:
mutex_unlock(&pmc->powergates_lock);
return err;
}
EXPORT_SYMBOL(tegra_io_pad_power_disable);
int tegra_io_pad_set_voltage(enum tegra_io_pad id,
enum tegra_io_pad_voltage voltage)
{
const struct tegra_io_pad_soc *pad;
u32 value;
pad = tegra_io_pad_find(pmc, id);
if (!pad)
return -ENOENT;
if (pad->voltage == UINT_MAX)
return -ENOTSUPP;
mutex_lock(&pmc->powergates_lock);
/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
value = tegra_pmc_readl(PMC_PWR_DET);
value |= BIT(pad->voltage);
tegra_pmc_writel(value, PMC_PWR_DET);
/* update I/O voltage */
value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
if (voltage == TEGRA_IO_PAD_1800000UV)
value &= ~BIT(pad->voltage);
else
value |= BIT(pad->voltage);
tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
error:
mutex_unlock(&pmc->powergates_lock);
return err;
usleep_range(100, 250);
return 0;
}
EXPORT_SYMBOL(tegra_io_pad_set_voltage);
int tegra_io_pad_get_voltage(enum tegra_io_pad id)
{
const struct tegra_io_pad_soc *pad;
u32 value;
pad = tegra_io_pad_find(pmc, id);
if (!pad)
return -ENOENT;
if (pad->voltage == UINT_MAX)
return -ENOTSUPP;
value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
if ((value & BIT(pad->voltage)) == 0)
return TEGRA_IO_PAD_1800000UV;
return TEGRA_IO_PAD_3300000UV;
}
EXPORT_SYMBOL(tegra_io_pad_get_voltage);
/**
* tegra_io_rail_power_on() - enable power to I/O rail
* @id: Tegra I/O pad ID for which to enable power
*
* See also: tegra_io_pad_power_enable()
*/
int tegra_io_rail_power_on(unsigned int id)
{
return tegra_io_pad_power_enable(id);
}
EXPORT_SYMBOL(tegra_io_rail_power_on);
/**
* tegra_io_rail_power_off() - disable power to I/O rail
* @id: Tegra I/O pad ID for which to disable power
*
* See also: tegra_io_pad_power_disable()
*/
int tegra_io_rail_power_off(unsigned int id)
{
unsigned long request, status;
unsigned int bit;
int err;
mutex_lock(&pmc->powergates_lock);
err = tegra_io_rail_prepare(id, &request, &status, &bit);
if (err) {
pr_info("tegra_io_rail_prepare() failed: %d\n", err);
goto error;
}
tegra_pmc_writel(IO_DPD_REQ_CODE_ON | BIT(bit), request);
err = tegra_io_rail_poll(status, BIT(bit), BIT(bit), 250);
if (err)
goto error;
tegra_io_rail_unprepare();
error:
mutex_unlock(&pmc->powergates_lock);
return err;
return tegra_io_pad_power_disable(id);
}
EXPORT_SYMBOL(tegra_io_rail_power_off);
@ -1454,6 +1588,39 @@ static const u8 tegra124_cpu_powergates[] = {
TEGRA_POWERGATE_CPU3,
};
static const struct tegra_io_pad_soc tegra124_io_pads[] = {
{ .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
};
static const struct tegra_pmc_soc tegra124_pmc_soc = {
.num_powergates = ARRAY_SIZE(tegra124_powergates),
.powergates = tegra124_powergates,
@ -1461,6 +1628,8 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
.cpu_powergates = tegra124_cpu_powergates,
.has_tsense_reset = true,
.has_gpu_clamps = true,
.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
.io_pads = tegra124_io_pads,
};
static const char * const tegra210_powergates[] = {
@ -1497,6 +1666,47 @@ static const u8 tegra210_cpu_powergates[] = {
TEGRA_POWERGATE_CPU3,
};
static const struct tegra_io_pad_soc tegra210_io_pads[] = {
{ .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
{ .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
{ .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
{ .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
{ .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
{ .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
{ .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
{ .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
{ .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
{ .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
{ .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
{ .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
{ .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
{ .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
};
static const struct tegra_pmc_soc tegra210_pmc_soc = {
.num_powergates = ARRAY_SIZE(tegra210_powergates),
.powergates = tegra210_powergates,
@ -1504,6 +1714,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.cpu_powergates = tegra210_cpu_powergates,
.has_tsense_reset = true,
.has_gpu_clamps = true,
.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
.io_pads = tegra210_io_pads,
};
static const struct of_device_id tegra_pmc_match[] = {

940
include/dt-bindings/clock/tegra186-clock.h Normal file
View File

@ -0,0 +1,940 @@
/** @file */
#ifndef _MACH_T186_CLK_T186_H
#define _MACH_T186_CLK_T186_H
/**
* @defgroup clock_ids Clock Identifiers
* @{
* @defgroup extern_input external input clocks
* @{
* @def TEGRA186_CLK_OSC
* @def TEGRA186_CLK_CLK_32K
* @def TEGRA186_CLK_DTV_INPUT
* @def TEGRA186_CLK_SOR0_PAD_CLKOUT
* @def TEGRA186_CLK_SOR1_PAD_CLKOUT
* @def TEGRA186_CLK_I2S1_SYNC_INPUT
* @def TEGRA186_CLK_I2S2_SYNC_INPUT
* @def TEGRA186_CLK_I2S3_SYNC_INPUT
* @def TEGRA186_CLK_I2S4_SYNC_INPUT
* @def TEGRA186_CLK_I2S5_SYNC_INPUT
* @def TEGRA186_CLK_I2S6_SYNC_INPUT
* @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
* @}
*
* @defgroup extern_output external output clocks
* @{
* @def TEGRA186_CLK_EXTPERIPH1
* @def TEGRA186_CLK_EXTPERIPH2
* @def TEGRA186_CLK_EXTPERIPH3
* @def TEGRA186_CLK_EXTPERIPH4
* @}
*
* @defgroup display_clks display related clocks
* @{
* @def TEGRA186_CLK_CEC
* @def TEGRA186_CLK_DSIC
* @def TEGRA186_CLK_DSIC_LP
* @def TEGRA186_CLK_DSID
* @def TEGRA186_CLK_DSID_LP
* @def TEGRA186_CLK_DPAUX1
* @def TEGRA186_CLK_DPAUX
* @def TEGRA186_CLK_HDA2HDMICODEC
* @def TEGRA186_CLK_NVDISPLAY_DISP
* @def TEGRA186_CLK_NVDISPLAY_DSC
* @def TEGRA186_CLK_NVDISPLAY_P0
* @def TEGRA186_CLK_NVDISPLAY_P1
* @def TEGRA186_CLK_NVDISPLAY_P2
* @def TEGRA186_CLK_NVDISPLAYHUB
* @def TEGRA186_CLK_SOR_SAFE
* @def TEGRA186_CLK_SOR0
* @def TEGRA186_CLK_SOR0_OUT
* @def TEGRA186_CLK_SOR1
* @def TEGRA186_CLK_SOR1_OUT
* @def TEGRA186_CLK_DSI
* @def TEGRA186_CLK_MIPI_CAL
* @def TEGRA186_CLK_DSIA_LP
* @def TEGRA186_CLK_DSIB
* @def TEGRA186_CLK_DSIB_LP
* @}
*
* @defgroup camera_clks camera related clocks
* @{
* @def TEGRA186_CLK_NVCSI
* @def TEGRA186_CLK_NVCSILP
* @def TEGRA186_CLK_VI
* @}
*
* @defgroup audio_clks audio related clocks
* @{
* @def TEGRA186_CLK_ACLK
* @def TEGRA186_CLK_ADSP
* @def TEGRA186_CLK_ADSPNEON
* @def TEGRA186_CLK_AHUB
* @def TEGRA186_CLK_APE
* @def TEGRA186_CLK_APB2APE
* @def TEGRA186_CLK_AUD_MCLK
* @def TEGRA186_CLK_DMIC1
* @def TEGRA186_CLK_DMIC2
* @def TEGRA186_CLK_DMIC3
* @def TEGRA186_CLK_DMIC4
* @def TEGRA186_CLK_DSPK1
* @def TEGRA186_CLK_DSPK2
* @def TEGRA186_CLK_HDA
* @def TEGRA186_CLK_HDA2CODEC_2X
* @def TEGRA186_CLK_I2S1
* @def TEGRA186_CLK_I2S2
* @def TEGRA186_CLK_I2S3
* @def TEGRA186_CLK_I2S4
* @def TEGRA186_CLK_I2S5
* @def TEGRA186_CLK_I2S6
* @def TEGRA186_CLK_MAUD
* @def TEGRA186_CLK_PLL_A_OUT0
* @def TEGRA186_CLK_SPDIF_DOUBLER
* @def TEGRA186_CLK_SPDIF_IN
* @def TEGRA186_CLK_SPDIF_OUT
* @def TEGRA186_CLK_SYNC_DMIC1
* @def TEGRA186_CLK_SYNC_DMIC2
* @def TEGRA186_CLK_SYNC_DMIC3
* @def TEGRA186_CLK_SYNC_DMIC4
* @def TEGRA186_CLK_SYNC_DMIC5
* @def TEGRA186_CLK_SYNC_DSPK1
* @def TEGRA186_CLK_SYNC_DSPK2
* @def TEGRA186_CLK_SYNC_I2S1
* @def TEGRA186_CLK_SYNC_I2S2
* @def TEGRA186_CLK_SYNC_I2S3
* @def TEGRA186_CLK_SYNC_I2S4
* @def TEGRA186_CLK_SYNC_I2S5
* @def TEGRA186_CLK_SYNC_I2S6
* @def TEGRA186_CLK_SYNC_SPDIF
* @}
*
* @defgroup uart_clks UART clocks
* @{
* @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
* @def TEGRA186_CLK_UARTA
* @def TEGRA186_CLK_UARTB
* @def TEGRA186_CLK_UARTC
* @def TEGRA186_CLK_UARTD
* @def TEGRA186_CLK_UARTE
* @def TEGRA186_CLK_UARTF
* @def TEGRA186_CLK_UARTG
* @def TEGRA186_CLK_UART_FST_MIPI_CAL
* @}
*
* @defgroup i2c_clks I2C clocks
* @{
* @def TEGRA186_CLK_AON_I2C_SLOW
* @def TEGRA186_CLK_I2C1
* @def TEGRA186_CLK_I2C2
* @def TEGRA186_CLK_I2C3
* @def TEGRA186_CLK_I2C4
* @def TEGRA186_CLK_I2C5
* @def TEGRA186_CLK_I2C6
* @def TEGRA186_CLK_I2C8
* @def TEGRA186_CLK_I2C9
* @def TEGRA186_CLK_I2C1
* @def TEGRA186_CLK_I2C12
* @def TEGRA186_CLK_I2C13
* @def TEGRA186_CLK_I2C14
* @def TEGRA186_CLK_I2C_SLOW
* @def TEGRA186_CLK_VI_I2C
* @}
*
* @defgroup spi_clks SPI clocks
* @{
* @def TEGRA186_CLK_SPI1
* @def TEGRA186_CLK_SPI2
* @def TEGRA186_CLK_SPI3
* @def TEGRA186_CLK_SPI4
* @}
*
* @defgroup storage storage related clocks
* @{
* @def TEGRA186_CLK_SATA
* @def TEGRA186_CLK_SATA_OOB
* @def TEGRA186_CLK_SATA_IOBIST
* @def TEGRA186_CLK_SDMMC_LEGACY_TM
* @def TEGRA186_CLK_SDMMC1
* @def TEGRA186_CLK_SDMMC2
* @def TEGRA186_CLK_SDMMC3
* @def TEGRA186_CLK_SDMMC4
* @def TEGRA186_CLK_QSPI
* @def TEGRA186_CLK_QSPI_OUT
* @def TEGRA186_CLK_UFSDEV_REF
* @def TEGRA186_CLK_UFSHC
* @}
*
* @defgroup pwm_clks PWM clocks
* @{
* @def TEGRA186_CLK_PWM1
* @def TEGRA186_CLK_PWM2
* @def TEGRA186_CLK_PWM3
* @def TEGRA186_CLK_PWM4
* @def TEGRA186_CLK_PWM5
* @def TEGRA186_CLK_PWM6
* @def TEGRA186_CLK_PWM7
* @def TEGRA186_CLK_PWM8
* @}
*
* @defgroup plls PLLs and related clocks
* @{
* @def TEGRA186_CLK_PLLREFE_OUT_GATED
* @def TEGRA186_CLK_PLLREFE_OUT1
* @def TEGRA186_CLK_PLLD_OUT1
* @def TEGRA186_CLK_PLLP_OUT0
* @def TEGRA186_CLK_PLLP_OUT5
* @def TEGRA186_CLK_PLLA
* @def TEGRA186_CLK_PLLE_PWRSEQ
* @def TEGRA186_CLK_PLLA_OUT1
* @def TEGRA186_CLK_PLLREFE_REF
* @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
* @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
* @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
* @def TEGRA186_CLK_PLLREFE_PEX
* @def TEGRA186_CLK_PLLREFE_IDDQ
* @def TEGRA186_CLK_PLLC_OUT_AON
* @def TEGRA186_CLK_PLLC_OUT_ISP
* @def TEGRA186_CLK_PLLC_OUT_VE
* @def TEGRA186_CLK_PLLC4_OUT
* @def TEGRA186_CLK_PLLREFE_OUT
* @def TEGRA186_CLK_PLLREFE_PLL_REF
* @def TEGRA186_CLK_PLLE
* @def TEGRA186_CLK_PLLC
* @def TEGRA186_CLK_PLLP
* @def TEGRA186_CLK_PLLD
* @def TEGRA186_CLK_PLLD2
* @def TEGRA186_CLK_PLLREFE_VCO
* @def TEGRA186_CLK_PLLC2
* @def TEGRA186_CLK_PLLC3
* @def TEGRA186_CLK_PLLDP
* @def TEGRA186_CLK_PLLC4_VCO
* @def TEGRA186_CLK_PLLA1
* @def TEGRA186_CLK_PLLNVCSI
* @def TEGRA186_CLK_PLLDISPHUB
* @def TEGRA186_CLK_PLLD3
* @def TEGRA186_CLK_PLLBPMPCAM
* @def TEGRA186_CLK_PLLAON
* @def TEGRA186_CLK_PLLU
* @def TEGRA186_CLK_PLLC4_VCO_DIV2
* @def TEGRA186_CLK_PLL_REF
* @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
* @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
* @def TEGRA186_CLK_PLL_U_48M
* @def TEGRA186_CLK_PLL_U_480M
* @def TEGRA186_CLK_PLLC4_OUT0
* @def TEGRA186_CLK_PLLC4_OUT1
* @def TEGRA186_CLK_PLLC4_OUT2
* @def TEGRA186_CLK_PLLC4_OUT_MUX
* @def TEGRA186_CLK_DFLLDISP_DIV
* @def TEGRA186_CLK_PLLDISPHUB_DIV
* @def TEGRA186_CLK_PLLP_DIV8
* @}
*
* @defgroup nafll_clks NAFLL clock sources
* @{
* @def TEGRA186_CLK_NAFLL_AXI_CBB
* @def TEGRA186_CLK_NAFLL_BCPU
* @def TEGRA186_CLK_NAFLL_BPMP
* @def TEGRA186_CLK_NAFLL_DISP
* @def TEGRA186_CLK_NAFLL_GPU
* @def TEGRA186_CLK_NAFLL_ISP
* @def TEGRA186_CLK_NAFLL_MCPU
* @def TEGRA186_CLK_NAFLL_NVDEC
* @def TEGRA186_CLK_NAFLL_NVENC
* @def TEGRA186_CLK_NAFLL_NVJPG
* @def TEGRA186_CLK_NAFLL_SCE
* @def TEGRA186_CLK_NAFLL_SE
* @def TEGRA186_CLK_NAFLL_TSEC
* @def TEGRA186_CLK_NAFLL_TSECB
* @def TEGRA186_CLK_NAFLL_VI
* @def TEGRA186_CLK_NAFLL_VIC
* @}
*
* @defgroup mphy MPHY related clocks
* @{
* @def TEGRA186_CLK_MPHY_L0_RX_SYMB
* @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
* @def TEGRA186_CLK_MPHY_L0_TX_SYMB
* @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
* @def TEGRA186_CLK_MPHY_L0_RX_ANA
* @def TEGRA186_CLK_MPHY_L1_RX_ANA
* @def TEGRA186_CLK_MPHY_IOBIST
* @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
* @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
* @}
*
* @defgroup eavb EAVB related clocks
* @{
* @def TEGRA186_CLK_EQOS_AXI
* @def TEGRA186_CLK_EQOS_PTP_REF
* @def TEGRA186_CLK_EQOS_RX
* @def TEGRA186_CLK_EQOS_RX_INPUT
* @def TEGRA186_CLK_EQOS_TX
* @}
*
* @defgroup usb USB related clocks
* @{
* @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
* @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
* @def TEGRA186_CLK_HSIC_TRK
* @def TEGRA186_CLK_USB2_TRK
* @def TEGRA186_CLK_USB2_HSIC_TRK
* @def TEGRA186_CLK_XUSB_CORE_SS
* @def TEGRA186_CLK_XUSB_CORE_DEV
* @def TEGRA186_CLK_XUSB_FALCON
* @def TEGRA186_CLK_XUSB_FS
* @def TEGRA186_CLK_XUSB
* @def TEGRA186_CLK_XUSB_DEV
* @def TEGRA186_CLK_XUSB_HOST
* @def TEGRA186_CLK_XUSB_SS
* @}
*
* @defgroup bigblock compute block related clocks
* @{
* @def TEGRA186_CLK_GPCCLK
* @def TEGRA186_CLK_GPC2CLK
* @def TEGRA186_CLK_GPU
* @def TEGRA186_CLK_HOST1X
* @def TEGRA186_CLK_ISP
* @def TEGRA186_CLK_NVDEC
* @def TEGRA186_CLK_NVENC
* @def TEGRA186_CLK_NVJPG
* @def TEGRA186_CLK_SE
* @def TEGRA186_CLK_TSEC
* @def TEGRA186_CLK_TSECB
* @def TEGRA186_CLK_VIC
* @}
*
* @defgroup can CAN bus related clocks
* @{
* @def TEGRA186_CLK_CAN1
* @def TEGRA186_CLK_CAN1_HOST
* @def TEGRA186_CLK_CAN2
* @def TEGRA186_CLK_CAN2_HOST
* @}
*
* @defgroup system basic system clocks
* @{
* @def TEGRA186_CLK_ACTMON
* @def TEGRA186_CLK_AON_APB
* @def TEGRA186_CLK_AON_CPU_NIC
* @def TEGRA186_CLK_AON_NIC
* @def TEGRA186_CLK_AXI_CBB
* @def TEGRA186_CLK_BPMP_APB
* @def TEGRA186_CLK_BPMP_CPU_NIC
* @def TEGRA186_CLK_BPMP_NIC_RATE
* @def TEGRA186_CLK_CLK_M
* @def TEGRA186_CLK_EMC
* @def TEGRA186_CLK_MSS_ENCRYPT
* @def TEGRA186_CLK_SCE_APB
* @def TEGRA186_CLK_SCE_CPU_NIC
* @def TEGRA186_CLK_SCE_NIC
* @def TEGRA186_CLK_TSC
* @}
*
* @defgroup pcie_clks PCIe related clocks
* @{
* @def TEGRA186_CLK_AFI
* @def TEGRA186_CLK_PCIE
* @def TEGRA186_CLK_PCIE2_IOBIST
* @def TEGRA186_CLK_PCIERX0
* @def TEGRA186_CLK_PCIERX1
* @def TEGRA186_CLK_PCIERX2
* @def TEGRA186_CLK_PCIERX3
* @def TEGRA186_CLK_PCIERX4
* @}
*/
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA186_CLK_FUSE 0
/**
* @brief It's not what you think
* @details output of gate CLK_ENB_GPU. This output connects to the GPU
* pwrclk. @warning: This is almost certainly not the clock you think
* it is. If you're looking for the clock of the graphics engine, see
* TEGRA186_GPCCLK
*/
#define TEGRA186_CLK_GPU 1
/** @brief output of gate CLK_ENB_PCIE */
#define TEGRA186_CLK_PCIE 3
/** @brief output of the divider IPFS_CLK_DIVISOR */
#define TEGRA186_CLK_AFI 4
/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
#define TEGRA186_CLK_PCIE2_IOBIST 5
/** @brief output of gate CLK_ENB_PCIERX0*/
#define TEGRA186_CLK_PCIERX0 6
/** @brief output of gate CLK_ENB_PCIERX1*/
#define TEGRA186_CLK_PCIERX1 7
/** @brief output of gate CLK_ENB_PCIERX2*/
#define TEGRA186_CLK_PCIERX2 8
/** @brief output of gate CLK_ENB_PCIERX3*/
#define TEGRA186_CLK_PCIERX3 9
/** @brief output of gate CLK_ENB_PCIERX4*/
#define TEGRA186_CLK_PCIERX4 10
/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
#define TEGRA186_CLK_PLLC_OUT_ISP 11
/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
#define TEGRA186_CLK_PLLC_OUT_VE 12
/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
#define TEGRA186_CLK_PLLC_OUT_AON 13
/** @brief output of gate CLK_ENB_SOR_SAFE */
#define TEGRA186_CLK_SOR_SAFE 39
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
#define TEGRA186_CLK_I2S2 42
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
#define TEGRA186_CLK_I2S3 43
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
#define TEGRA186_CLK_SPDIF_IN 44
/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
#define TEGRA186_CLK_SPDIF_DOUBLER 45
/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
#define TEGRA186_CLK_SPI3 46
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
#define TEGRA186_CLK_I2C1 47
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
#define TEGRA186_CLK_I2C5 48
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
#define TEGRA186_CLK_SPI1 49
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
#define TEGRA186_CLK_ISP 50
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
#define TEGRA186_CLK_VI 51
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
#define TEGRA186_CLK_SDMMC1 52
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
#define TEGRA186_CLK_SDMMC2 53
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA186_CLK_SDMMC4 54
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA186_CLK_UARTA 55
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
#define TEGRA186_CLK_UARTB 56
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
#define TEGRA186_CLK_HOST1X 57
/**
* @brief controls the EMC clock frequency.
* @details Doing a clk_set_rate on this clock will select the
* appropriate clock source, program the source rate and execute a
* specific sequence to switch to the new clock source for both memory
* controllers. This can be used to control the balance between memory
* throughput and memory controller power.
*/
#define TEGRA186_CLK_EMC 58
/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
#define TEGRA186_CLK_EXTPERIPH4 73
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
#define TEGRA186_CLK_SPI4 74
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
#define TEGRA186_CLK_I2C3 75
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
#define TEGRA186_CLK_SDMMC3 76
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
#define TEGRA186_CLK_UARTD 77
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
#define TEGRA186_CLK_I2S1 79
/** output of gate CLK_ENB_DTV */
#define TEGRA186_CLK_DTV 80
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
#define TEGRA186_CLK_TSEC 81
/** @brief output of gate CLK_ENB_DP2 */
#define TEGRA186_CLK_DP2 82
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
#define TEGRA186_CLK_I2S4 84
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
#define TEGRA186_CLK_I2S5 85
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
#define TEGRA186_CLK_I2C4 86
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
#define TEGRA186_CLK_AHUB 87
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
#define TEGRA186_CLK_HDA2CODEC_2X 88
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
#define TEGRA186_CLK_EXTPERIPH1 89
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
#define TEGRA186_CLK_EXTPERIPH2 90
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
#define TEGRA186_CLK_EXTPERIPH3 91
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
#define TEGRA186_CLK_I2C_SLOW 92
/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
#define TEGRA186_CLK_SOR1 93
/** @brief output of gate CLK_ENB_CEC */
#define TEGRA186_CLK_CEC 94
/** @brief output of gate CLK_ENB_DPAUX1 */
#define TEGRA186_CLK_DPAUX1 95
/** @brief output of gate CLK_ENB_DPAUX */
#define TEGRA186_CLK_DPAUX 96
/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
#define TEGRA186_CLK_SOR0 97
/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
#define TEGRA186_CLK_HDA2HDMICODEC 98
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
#define TEGRA186_CLK_SATA 99
/** @brief output of gate CLK_ENB_SATA_OOB */
#define TEGRA186_CLK_SATA_OOB 100
/** @brief output of gate CLK_ENB_SATA_IOBIST */
#define TEGRA186_CLK_SATA_IOBIST 101
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
#define TEGRA186_CLK_HDA 102
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
#define TEGRA186_CLK_SE 103
/** @brief output of gate CLK_ENB_APB2APE */
#define TEGRA186_CLK_APB2APE 104
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
#define TEGRA186_CLK_APE 105
/** @brief output of gate CLK_ENB_IQC1 */
#define TEGRA186_CLK_IQC1 106
/** @brief output of gate CLK_ENB_IQC2 */
#define TEGRA186_CLK_IQC2 107
/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
#define TEGRA186_CLK_PLLREFE_OUT 108
/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
#define TEGRA186_CLK_PLLREFE_PLL_REF 109
/** @brief output of gate CLK_ENB_PLLC4_OUT */
#define TEGRA186_CLK_PLLC4_OUT 110
/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB 111
/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_DEV 112
/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_HOST 113
/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_SS 114
/** @brief output of gate CLK_ENB_DSI */
#define TEGRA186_CLK_DSI 115
/** @brief output of gate CLK_ENB_MIPI_CAL */
#define TEGRA186_CLK_MIPI_CAL 116
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
#define TEGRA186_CLK_DSIA_LP 117
/** @brief output of gate CLK_ENB_DSIB */
#define TEGRA186_CLK_DSIB 118
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
#define TEGRA186_CLK_DSIB_LP 119
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
#define TEGRA186_CLK_DMIC1 122
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
#define TEGRA186_CLK_DMIC2 123
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
#define TEGRA186_CLK_AUD_MCLK 124
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
#define TEGRA186_CLK_I2C6 125
/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
#define TEGRA186_CLK_VIC 127
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
#define TEGRA186_CLK_NVDEC 129
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
#define TEGRA186_CLK_NVJPG 130
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
#define TEGRA186_CLK_NVENC 131
/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
#define TEGRA186_CLK_QSPI 132
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
#define TEGRA186_CLK_VI_I2C 133
/** @brief output of gate CLK_ENB_HSIC_TRK */
#define TEGRA186_CLK_HSIC_TRK 134
/** @brief output of gate CLK_ENB_USB2_TRK */
#define TEGRA186_CLK_USB2_TRK 135
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
#define TEGRA186_CLK_MAUD 136
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
#define TEGRA186_CLK_TSECB 137
/** @brief output of gate CLK_ENB_ADSP */
#define TEGRA186_CLK_ADSP 138
/** @brief output of gate CLK_ENB_ADSPNEON */
#define TEGRA186_CLK_ADSPNEON 139
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
#define TEGRA186_CLK_MPHY_IOBIST 146
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
#define TEGRA186_CLK_AXI_CBB 149
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
#define TEGRA186_CLK_DMIC3 150
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
#define TEGRA186_CLK_DMIC4 151
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
#define TEGRA186_CLK_DSPK1 152
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
#define TEGRA186_CLK_DSPK2 153
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
#define TEGRA186_CLK_I2S6 154
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
#define TEGRA186_CLK_NVDISPLAY_P0 155
/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
#define TEGRA186_CLK_NVDISPLAY_DISP 156
/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
#define TEGRA186_CLK_NVDISPLAY_DSC 157
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
#define TEGRA186_CLK_NVDISPLAYHUB 158
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
#define TEGRA186_CLK_NVDISPLAY_P1 159
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
#define TEGRA186_CLK_NVDISPLAY_P2 160
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
#define TEGRA186_CLK_TACH 166
/** @brief output of gate CLK_ENB_EQOS */
#define TEGRA186_CLK_EQOS_AXI 167
/** @brief output of gate CLK_ENB_EQOS_RX */
#define TEGRA186_CLK_EQOS_RX 168
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
#define TEGRA186_CLK_UFSHC 178
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
#define TEGRA186_CLK_UFSDEV_REF 179
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
#define TEGRA186_CLK_NVCSI 180
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
#define TEGRA186_CLK_NVCSILP 181
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
#define TEGRA186_CLK_I2C7 182
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
#define TEGRA186_CLK_I2C9 183
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
#define TEGRA186_CLK_I2C12 184
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
#define TEGRA186_CLK_I2C13 185
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
#define TEGRA186_CLK_I2C14 186
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
#define TEGRA186_CLK_PWM1 187
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
#define TEGRA186_CLK_PWM2 188
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
#define TEGRA186_CLK_PWM3 189
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
#define TEGRA186_CLK_PWM5 190
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
#define TEGRA186_CLK_PWM6 191
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
#define TEGRA186_CLK_PWM7 192
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
#define TEGRA186_CLK_PWM8 193
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
#define TEGRA186_CLK_UARTE 194
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
#define TEGRA186_CLK_UARTF 195
/** @deprecated */
#define TEGRA186_CLK_DBGAPB 196
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
#define TEGRA186_CLK_BPMP_CPU_NIC 197
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
#define TEGRA186_CLK_BPMP_APB 199
/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
#define TEGRA186_CLK_ACTMON 201
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
#define TEGRA186_CLK_AON_CPU_NIC 208
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
#define TEGRA186_CLK_CAN1 210
/** @brief output of gate CLK_ENB_CAN1_HOST */
#define TEGRA186_CLK_CAN1_HOST 211
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
#define TEGRA186_CLK_CAN2 212
/** @brief output of gate CLK_ENB_CAN2_HOST */
#define TEGRA186_CLK_CAN2_HOST 213
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
#define TEGRA186_CLK_AON_APB 214
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
#define TEGRA186_CLK_UARTC 215
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
#define TEGRA186_CLK_UARTG 216
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
#define TEGRA186_CLK_I2C2 218
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
#define TEGRA186_CLK_I2C8 219
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
#define TEGRA186_CLK_I2C10 220
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
#define TEGRA186_CLK_AON_I2C_SLOW 221
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
#define TEGRA186_CLK_SPI2 222
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
#define TEGRA186_CLK_DMIC5 223
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
#define TEGRA186_CLK_AON_TOUCH 224
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
#define TEGRA186_CLK_PWM4 225
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
#define TEGRA186_CLK_TSC 226
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
#define TEGRA186_CLK_MSS_ENCRYPT 227
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
#define TEGRA186_CLK_SCE_CPU_NIC 228
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
#define TEGRA186_CLK_SCE_APB 230
/** @brief output of gate CLK_ENB_DSIC */
#define TEGRA186_CLK_DSIC 231
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
#define TEGRA186_CLK_DSIC_LP 232
/** @brief output of gate CLK_ENB_DSID */
#define TEGRA186_CLK_DSID 233
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
#define TEGRA186_CLK_DSID_LP 234
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
#define TEGRA186_CLK_SPDIF_OUT 238
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
#define TEGRA186_CLK_EQOS_PTP_REF 239
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
#define TEGRA186_CLK_EQOS_TX 240
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
#define TEGRA186_CLK_USB2_HSIC_TRK 241
/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_CORE_SS 242
/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_CORE_DEV 243
/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_FALCON 244
/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_FS 245
/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
#define TEGRA186_CLK_PLL_A_OUT0 246
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
#define TEGRA186_CLK_SYNC_I2S1 247
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
#define TEGRA186_CLK_SYNC_I2S2 248
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
#define TEGRA186_CLK_SYNC_I2S3 249
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
#define TEGRA186_CLK_SYNC_I2S4 250
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
#define TEGRA186_CLK_SYNC_I2S5 251
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
#define TEGRA186_CLK_SYNC_I2S6 252
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
#define TEGRA186_CLK_SYNC_DSPK1 253
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
#define TEGRA186_CLK_SYNC_DSPK2 254
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
#define TEGRA186_CLK_SYNC_DMIC1 255
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
#define TEGRA186_CLK_SYNC_DMIC2 256
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
#define TEGRA186_CLK_SYNC_DMIC3 257
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
#define TEGRA186_CLK_SYNC_DMIC4 259
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
#define TEGRA186_CLK_SYNC_SPDIF 260
/** @brief output of gate CLK_ENB_PLLREFE_OUT */
#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
* * VCO/pdiv defined by this clock object
* * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
*/
#define TEGRA186_CLK_PLLREFE_OUT1 262
#define TEGRA186_CLK_PLLD_OUT1 267
/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
#define TEGRA186_CLK_PLLP_OUT0 269
/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
#define TEGRA186_CLK_PLLP_OUT5 270
/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
#define TEGRA186_CLK_PLLA 271
/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
#define TEGRA186_CLK_ACLK 273
/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLL_U_48M 274
/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLL_U_480M 275
/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
#define TEGRA186_CLK_PLLC4_OUT0 276
/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
#define TEGRA186_CLK_PLLC4_OUT1 277
/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
#define TEGRA186_CLK_PLLC4_OUT2 278
/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
#define TEGRA186_CLK_PLLC4_OUT_MUX 279
/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
#define TEGRA186_CLK_DFLLDISP_DIV 284
/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
#define TEGRA186_CLK_PLLDISPHUB_DIV 285
/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
#define TEGRA186_CLK_PLLP_DIV8 286
/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
#define TEGRA186_CLK_BPMP_NIC 287
/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
#define TEGRA186_CLK_PLL_A_OUT1 288
/** @deprecated */
#define TEGRA186_CLK_GPC2CLK 289
/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
#define TEGRA186_CLK_KFUSE 293
/**
* @brief controls the PLLE hardware sequencer.
* @details This clock only has enable and disable methods. When the
* PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
* hw based on the control signals from the PCIe, SATA and XUSB
* clocks. When the PLLE hw sequencer is disabled, the state of PLLE
* is controlled by sw using clk_enable/clk_disable on
* TEGRA186_CLK_PLLE.
*/
#define TEGRA186_CLK_PLLE_PWRSEQ 294
/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLLREFE_REF 295
/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
#define TEGRA186_CLK_SOR0_OUT 296
/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
#define TEGRA186_CLK_SOR1_OUT 297
/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
/** @brief controls the UPHY_PLL0 hardware sqeuencer */
#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
/** @brief controls the UPHY_PLL1 hardware sqeuencer */
#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
#define TEGRA186_CLK_PLLREFE_PEX 307
/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
#define TEGRA186_CLK_PLLREFE_IDDQ 308
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
#define TEGRA186_CLK_QSPI_OUT 309
/**
* @brief GPC2CLK-div-2
* @details fixed /2 divider. Output frequency is
* TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
* frequency at which the GPU graphics engine runs. */
#define TEGRA186_CLK_GPCCLK 310
/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
#define TEGRA186_CLK_AON_NIC 450
/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
#define TEGRA186_CLK_SCE_NIC 451
/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
#define TEGRA186_CLK_PLLE 512
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
#define TEGRA186_CLK_PLLC 513
/** Fixed 408MHz PLL for use by peripheral clocks */
#define TEGRA186_CLK_PLLP 516
/** @deprecated */
#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
#define TEGRA186_CLK_PLLD 518
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
#define TEGRA186_CLK_PLLD2 519
/**
* @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
* @details Note that this clock only controls the VCO output, before
* the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
* information.
*/
#define TEGRA186_CLK_PLLREFE_VCO 520
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
#define TEGRA186_CLK_PLLC2 521
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
#define TEGRA186_CLK_PLLC3 522
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
#define TEGRA186_CLK_PLLDP 523
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA186_CLK_PLLC4_VCO 524
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
#define TEGRA186_CLK_PLLA1 525
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
#define TEGRA186_CLK_PLLNVCSI 526
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
#define TEGRA186_CLK_PLLDISPHUB 527
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
#define TEGRA186_CLK_PLLD3 528
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
#define TEGRA186_CLK_PLLBPMPCAM 531
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
#define TEGRA186_CLK_PLLAON 532
/** Fixed frequency 960MHz PLL for USB and EAVB */
#define TEGRA186_CLK_PLLU 533
/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
/** @brief NAFLL clock source for AXI_CBB */
#define TEGRA186_CLK_NAFLL_AXI_CBB 564
/** @brief NAFLL clock source for BPMP */
#define TEGRA186_CLK_NAFLL_BPMP 565
/** @brief NAFLL clock source for ISP */
#define TEGRA186_CLK_NAFLL_ISP 566
/** @brief NAFLL clock source for NVDEC */
#define TEGRA186_CLK_NAFLL_NVDEC 567
/** @brief NAFLL clock source for NVENC */
#define TEGRA186_CLK_NAFLL_NVENC 568
/** @brief NAFLL clock source for NVJPG */
#define TEGRA186_CLK_NAFLL_NVJPG 569
/** @brief NAFLL clock source for SCE */
#define TEGRA186_CLK_NAFLL_SCE 570
/** @brief NAFLL clock source for SE */
#define TEGRA186_CLK_NAFLL_SE 571
/** @brief NAFLL clock source for TSEC */
#define TEGRA186_CLK_NAFLL_TSEC 572
/** @brief NAFLL clock source for TSECB */
#define TEGRA186_CLK_NAFLL_TSECB 573
/** @brief NAFLL clock source for VI */
#define TEGRA186_CLK_NAFLL_VI 574
/** @brief NAFLL clock source for VIC */
#define TEGRA186_CLK_NAFLL_VIC 575
/** @brief NAFLL clock source for DISP */
#define TEGRA186_CLK_NAFLL_DISP 576
/** @brief NAFLL clock source for GPU */
#define TEGRA186_CLK_NAFLL_GPU 577
/** @brief NAFLL clock source for M-CPU cluster */
#define TEGRA186_CLK_NAFLL_MCPU 578
/** @brief NAFLL clock source for B-CPU cluster */
#define TEGRA186_CLK_NAFLL_BCPU 579
/** @brief input from Tegra's CLK_32K_IN pad */
#define TEGRA186_CLK_CLK_32K 608
/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
#define TEGRA186_CLK_CLK_M 609
/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
#define TEGRA186_CLK_PLL_REF 610
/** @brief input from Tegra's XTAL_IN */
#define TEGRA186_CLK_OSC 612
/** @brief clock recovered from EAVB input */
#define TEGRA186_CLK_EQOS_RX_INPUT 613
/** @brief clock recovered from DTV input */
#define TEGRA186_CLK_DTV_INPUT 614
/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
/** @brief clock recovered from I2S1 input */
#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
/** @brief clock recovered from I2S2 input */
#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
/** @brief clock recovered from I2S3 input */
#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
/** @brief clock recovered from I2S4 input */
#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
/** @brief clock recovered from I2S5 input */
#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
/** @brief clock recovered from I2S6 input */
#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
/** @brief clock recovered from SPDIFIN input */
#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
/**
* @brief subject to change
* @details maximum clock identifier value plus one.
*/
#define TEGRA186_CLK_CLK_MAX 624
/** @} */
#endif

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include/dt-bindings/mailbox/tegra186-hsp.h Normal file
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/*
* This header provides constants for binding nvidia,tegra186-hsp.
*/
#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
/*
* These define the type of mailbox that is to be used (doorbell, shared
* mailbox, shared semaphore or arbitrated semaphore).
*/
#define TEGRA_HSP_MBOX_TYPE_DB 0x0
#define TEGRA_HSP_MBOX_TYPE_SM 0x1
#define TEGRA_HSP_MBOX_TYPE_SS 0x2
#define TEGRA_HSP_MBOX_TYPE_AS 0x3
/*
* These defines represent the bit associated with the given master ID in the
* doorbell registers.
*/
#define TEGRA_HSP_DB_MASTER_CCPLEX 17
#define TEGRA_HSP_DB_MASTER_BPMP 19
#endif

4
include/dt-bindings/pinctrl/qcom,pmic-gpio.h
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#define PMA8084_GPIO_S4 2
#define PMA8084_GPIO_L6 3
#define PM8994_GPIO_VPH 0
#define PM8994_GPIO_S4 2
#define PM8994_GPIO_L12 3
/* To be used with "function" */
#define PMIC_GPIO_FUNC_NORMAL "normal"
#define PMIC_GPIO_FUNC_PAIRED "paired"

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include/dt-bindings/pinctrl/qcom,pmic-mpp.h
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#define PMA8084_MPP_S4 2
#define PMA8084_MPP_L6 3
#define PM8994_MPP_VPH 0
/* Only supported for MPP_05-MPP_08 */
#define PM8994_MPP_L19 1
#define PM8994_MPP_S4 2
#define PM8994_MPP_L12 3
/*
* Analog Input - Set the source for analog input.
* To be used with "qcom,amux-route" property

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include/dt-bindings/power/tegra186-powergate.h Normal file
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/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
#define TEGRA186_POWER_DOMAIN_AUD 0
#define TEGRA186_POWER_DOMAIN_DFD 1
#define TEGRA186_POWER_DOMAIN_DISP 2
#define TEGRA186_POWER_DOMAIN_DISPB 3
#define TEGRA186_POWER_DOMAIN_DISPC 4
#define TEGRA186_POWER_DOMAIN_ISPA 5
#define TEGRA186_POWER_DOMAIN_NVDEC 6
#define TEGRA186_POWER_DOMAIN_NVJPG 7
#define TEGRA186_POWER_DOMAIN_MPE 8
#define TEGRA186_POWER_DOMAIN_PCX 9
#define TEGRA186_POWER_DOMAIN_SAX 10
#define TEGRA186_POWER_DOMAIN_VE 11
#define TEGRA186_POWER_DOMAIN_VIC 12
#define TEGRA186_POWER_DOMAIN_XUSBA 13
#define TEGRA186_POWER_DOMAIN_XUSBB 14
#define TEGRA186_POWER_DOMAIN_XUSBC 15
#define TEGRA186_POWER_DOMAIN_GPU 43
#define TEGRA186_POWER_DOMAIN_MAX 44
#endif

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include/dt-bindings/reset/oxsemi,ox810se.h Normal file
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/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_RESET_OXSEMI_OX810SE_H
#define DT_RESET_OXSEMI_OX810SE_H
#define RESET_ARM 0
#define RESET_COPRO 1
/* Reserved 2 */
/* Reserved 3 */
#define RESET_USBHS 4
#define RESET_USBHSPHY 5
#define RESET_MAC 6
#define RESET_PCI 7
#define RESET_DMA 8
#define RESET_DPE 9
#define RESET_DDR 10
#define RESET_SATA 11
#define RESET_SATA_LINK 12
#define RESET_SATA_PHY 13
/* Reserved 14 */
#define RESET_NAND 15
#define RESET_GPIO 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_MISC 19
#define RESET_I2S 20
#define RESET_AHB_MON 21
#define RESET_UART3 22
#define RESET_UART4 23
#define RESET_SGDMA 24
/* Reserved 25 */
/* Reserved 26 */
/* Reserved 27 */
/* Reserved 28 */
/* Reserved 29 */
/* Reserved 30 */
#define RESET_BUS 31
#endif /* DT_RESET_OXSEMI_OX810SE_H */

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include/dt-bindings/reset/oxsemi,ox820.h Normal file
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/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_RESET_OXSEMI_OX820_H
#define DT_RESET_OXSEMI_OX820_H
#define RESET_SCU 0
#define RESET_LEON 1
#define RESET_ARM0 2
#define RESET_ARM1 3
#define RESET_USBHS 4
#define RESET_USBPHYA 5
#define RESET_MAC 6
#define RESET_PCIEA 7
#define RESET_SGDMA 8
#define RESET_CIPHER 9
#define RESET_DDR 10
#define RESET_SATA 11
#define RESET_SATA_LINK 12
#define RESET_SATA_PHY 13
#define RESET_PCIEPHY 14
#define RESET_NAND 15
#define RESET_GPIO 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_MISC 19
#define RESET_I2S 20
#define RESET_SD 21
#define RESET_MAC_2 22
#define RESET_PCIEB 23
#define RESET_VIDEO 24
#define RESET_DDR_PHY 25
#define RESET_USBPHYB 26
#define RESET_USBDEV 27
/* Reserved 29 */
#define RESET_ARMDBG 29
#define RESET_PLLA 30
#define RESET_PLLB 31
#endif /* DT_RESET_OXSEMI_OX820_H */

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include/dt-bindings/reset/tegra186-reset.h Normal file
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/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _ABI_MACH_T186_RESET_T186_H_
#define _ABI_MACH_T186_RESET_T186_H_
#define TEGRA186_RESET_ACTMON 0
#define TEGRA186_RESET_AFI 1
#define TEGRA186_RESET_CEC 2
#define TEGRA186_RESET_CSITE 3
#define TEGRA186_RESET_DP2 4
#define TEGRA186_RESET_DPAUX 5
#define TEGRA186_RESET_DSI 6
#define TEGRA186_RESET_DSIB 7
#define TEGRA186_RESET_DTV 8
#define TEGRA186_RESET_DVFS 9
#define TEGRA186_RESET_ENTROPY 10
#define TEGRA186_RESET_EXTPERIPH1 11
#define TEGRA186_RESET_EXTPERIPH2 12
#define TEGRA186_RESET_EXTPERIPH3 13
#define TEGRA186_RESET_GPU 14
#define TEGRA186_RESET_HDA 15
#define TEGRA186_RESET_HDA2CODEC_2X 16
#define TEGRA186_RESET_HDA2HDMICODEC 17
#define TEGRA186_RESET_HOST1X 18
#define TEGRA186_RESET_I2C1 19
#define TEGRA186_RESET_I2C2 20
#define TEGRA186_RESET_I2C3 21
#define TEGRA186_RESET_I2C4 22
#define TEGRA186_RESET_I2C5 23
#define TEGRA186_RESET_I2C6 24
#define TEGRA186_RESET_ISP 25
#define TEGRA186_RESET_KFUSE 26
#define TEGRA186_RESET_LA 27
#define TEGRA186_RESET_MIPI_CAL 28
#define TEGRA186_RESET_PCIE 29
#define TEGRA186_RESET_PCIEXCLK 30
#define TEGRA186_RESET_SATA 31
#define TEGRA186_RESET_SATACOLD 32
#define TEGRA186_RESET_SDMMC1 33
#define TEGRA186_RESET_SDMMC2 34
#define TEGRA186_RESET_SDMMC3 35
#define TEGRA186_RESET_SDMMC4 36
#define TEGRA186_RESET_SE 37
#define TEGRA186_RESET_SOC_THERM 38
#define TEGRA186_RESET_SOR0 39
#define TEGRA186_RESET_SPI1 40
#define TEGRA186_RESET_SPI2 41
#define TEGRA186_RESET_SPI3 42
#define TEGRA186_RESET_SPI4 43
#define TEGRA186_RESET_TMR 44
#define TEGRA186_RESET_TRIG_SYS 45
#define TEGRA186_RESET_TSEC 46
#define TEGRA186_RESET_UARTA 47
#define TEGRA186_RESET_UARTB 48
#define TEGRA186_RESET_UARTC 49
#define TEGRA186_RESET_UARTD 50
#define TEGRA186_RESET_VI 51
#define TEGRA186_RESET_VIC 52
#define TEGRA186_RESET_XUSB_DEV 53
#define TEGRA186_RESET_XUSB_HOST 54
#define TEGRA186_RESET_XUSB_PADCTL 55
#define TEGRA186_RESET_XUSB_SS 56
#define TEGRA186_RESET_AON_APB 57
#define TEGRA186_RESET_AXI_CBB 58
#define TEGRA186_RESET_BPMP_APB 59
#define TEGRA186_RESET_CAN1 60
#define TEGRA186_RESET_CAN2 61
#define TEGRA186_RESET_DMIC5 62
#define TEGRA186_RESET_DSIC 63
#define TEGRA186_RESET_DSID 64
#define TEGRA186_RESET_EMC_EMC 65
#define TEGRA186_RESET_EMC_MEM 66
#define TEGRA186_RESET_EMCSB_EMC 67
#define TEGRA186_RESET_EMCSB_MEM 68
#define TEGRA186_RESET_EQOS 69
#define TEGRA186_RESET_GPCDMA 70
#define TEGRA186_RESET_GPIO_CTL0 71
#define TEGRA186_RESET_GPIO_CTL1 72
#define TEGRA186_RESET_GPIO_CTL2 73
#define TEGRA186_RESET_GPIO_CTL3 74
#define TEGRA186_RESET_GPIO_CTL4 75
#define TEGRA186_RESET_GPIO_CTL5 76
#define TEGRA186_RESET_I2C10 77
#define TEGRA186_RESET_I2C12 78
#define TEGRA186_RESET_I2C13 79
#define TEGRA186_RESET_I2C14 80
#define TEGRA186_RESET_I2C7 81
#define TEGRA186_RESET_I2C8 82
#define TEGRA186_RESET_I2C9 83
#define TEGRA186_RESET_JTAG2AXI 84
#define TEGRA186_RESET_MPHY_IOBIST 85
#define TEGRA186_RESET_MPHY_L0_RX 86
#define TEGRA186_RESET_MPHY_L0_TX 87
#define TEGRA186_RESET_NVCSI 88
#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89
#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90
#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91
#define TEGRA186_RESET_NVDISPLAY0_MISC 92
#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93
#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94
#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95
#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96
#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97
#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98
#define TEGRA186_RESET_PWM1 99
#define TEGRA186_RESET_PWM2 100
#define TEGRA186_RESET_PWM3 101
#define TEGRA186_RESET_PWM4 102
#define TEGRA186_RESET_PWM5 103
#define TEGRA186_RESET_PWM6 104
#define TEGRA186_RESET_PWM7 105
#define TEGRA186_RESET_PWM8 106
#define TEGRA186_RESET_SCE_APB 107
#define TEGRA186_RESET_SOR1 108
#define TEGRA186_RESET_TACH 109
#define TEGRA186_RESET_TSC 110
#define TEGRA186_RESET_UARTF 111
#define TEGRA186_RESET_UARTG 112
#define TEGRA186_RESET_UFSHC 113
#define TEGRA186_RESET_UFSHC_AXI_M 114
#define TEGRA186_RESET_UPHY 115
#define TEGRA186_RESET_ADSP 116
#define TEGRA186_RESET_ADSPDBG 117
#define TEGRA186_RESET_ADSPINTF 118
#define TEGRA186_RESET_ADSPNEON 119
#define TEGRA186_RESET_ADSPPERIPH 120
#define TEGRA186_RESET_ADSPSCU 121
#define TEGRA186_RESET_ADSPWDT 122
#define TEGRA186_RESET_APE 123
#define TEGRA186_RESET_DPAUX1 124
#define TEGRA186_RESET_NVDEC 125
#define TEGRA186_RESET_NVENC 126
#define TEGRA186_RESET_NVJPG 127
#define TEGRA186_RESET_PEX_USB_UPHY 128
#define TEGRA186_RESET_QSPI 129
#define TEGRA186_RESET_TSECB 130
#define TEGRA186_RESET_VI_I2C 131
#define TEGRA186_RESET_UARTE 132
#define TEGRA186_RESET_TOP_GTE 133
#define TEGRA186_RESET_SHSP 134
#define TEGRA186_RESET_PEX_USB_UPHY_L5 135
#define TEGRA186_RESET_PEX_USB_UPHY_L4 136
#define TEGRA186_RESET_PEX_USB_UPHY_L3 137
#define TEGRA186_RESET_PEX_USB_UPHY_L2 138
#define TEGRA186_RESET_PEX_USB_UPHY_L1 139
#define TEGRA186_RESET_PEX_USB_UPHY_L0 140
#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141
#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142
#define TEGRA186_RESET_TSCTNVI 143
#define TEGRA186_RESET_EXTPERIPH4 144
#define TEGRA186_RESET_DSIPADCTL 145
#define TEGRA186_RESET_AUD_MCLK 146
#define TEGRA186_RESET_MPHY_CLK_CTL 147
#define TEGRA186_RESET_MPHY_L1_RX 148
#define TEGRA186_RESET_MPHY_L1_TX 149
#define TEGRA186_RESET_UFSHC_LP 150
#define TEGRA186_RESET_BPMP_NIC 151
#define TEGRA186_RESET_BPMP_NSYSPORESET 152
#define TEGRA186_RESET_BPMP_NRESET 153
#define TEGRA186_RESET_BPMP_DBGRESETN 154
#define TEGRA186_RESET_BPMP_PRESETDBGN 155
#define TEGRA186_RESET_BPMP_PM 156
#define TEGRA186_RESET_BPMP_CVC 157
#define TEGRA186_RESET_BPMP_DMA 158
#define TEGRA186_RESET_BPMP_HSP 159
#define TEGRA186_RESET_TSCTNBPMP 160
#define TEGRA186_RESET_BPMP_TKE 161
#define TEGRA186_RESET_BPMP_GTE 162
#define TEGRA186_RESET_BPMP_PM_ACTMON 163
#define TEGRA186_RESET_AON_NIC 164
#define TEGRA186_RESET_AON_NSYSPORESET 165
#define TEGRA186_RESET_AON_NRESET 166
#define TEGRA186_RESET_AON_DBGRESETN 167
#define TEGRA186_RESET_AON_PRESETDBGN 168
#define TEGRA186_RESET_AON_ACTMON 169
#define TEGRA186_RESET_AOPM 170
#define TEGRA186_RESET_AOVC 171
#define TEGRA186_RESET_AON_DMA 172
#define TEGRA186_RESET_AON_GPIO 173
#define TEGRA186_RESET_AON_HSP 174
#define TEGRA186_RESET_TSCTNAON 175
#define TEGRA186_RESET_AON_TKE 176
#define TEGRA186_RESET_AON_GTE 177
#define TEGRA186_RESET_SCE_NIC 178
#define TEGRA186_RESET_SCE_NSYSPORESET 179
#define TEGRA186_RESET_SCE_NRESET 180
#define TEGRA186_RESET_SCE_DBGRESETN 181
#define TEGRA186_RESET_SCE_PRESETDBGN 182
#define TEGRA186_RESET_SCE_ACTMON 183
#define TEGRA186_RESET_SCE_PM 184
#define TEGRA186_RESET_SCE_DMA 185
#define TEGRA186_RESET_SCE_HSP 186
#define TEGRA186_RESET_TSCTNSCE 187
#define TEGRA186_RESET_SCE_TKE 188
#define TEGRA186_RESET_SCE_GTE 189
#define TEGRA186_RESET_SCE_CFG 190
#define TEGRA186_RESET_ADSP_ALL 191
/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
#define TEGRA186_RESET_UFSHC_LP_SEQ 192
#define TEGRA186_RESET_SIZE 193
#endif

13
include/linux/soc/qcom/wcnss_ctrl.h
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@ -3,6 +3,19 @@
#include <linux/soc/qcom/smd.h>
#if IS_ENABLED(CONFIG_QCOM_WCNSS_CTRL)
struct qcom_smd_channel *qcom_wcnss_open_channel(void *wcnss, const char *name, qcom_smd_cb_t cb);
#else
static inline struct qcom_smd_channel*
qcom_wcnss_open_channel(void *wcnss, const char *name, qcom_smd_cb_t cb)
{
WARN_ON(1);
return ERR_PTR(-ENXIO);
}
#endif
#endif

249
include/linux/soc/ti/ti_sci_protocol.h Normal file
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@ -0,0 +1,249 @@
/*
* Texas Instruments System Control Interface Protocol
*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __TISCI_PROTOCOL_H
#define __TISCI_PROTOCOL_H
/**
* struct ti_sci_version_info - version information structure
* @abi_major: Major ABI version. Change here implies risk of backward
* compatibility break.
* @abi_minor: Minor ABI version. Change here implies new feature addition,
* or compatible change in ABI.
* @firmware_revision: Firmware revision (not usually used).
* @firmware_description: Firmware description (not usually used).
*/
struct ti_sci_version_info {
u8 abi_major;
u8 abi_minor;
u16 firmware_revision;
char firmware_description[32];
};
struct ti_sci_handle;
/**
* struct ti_sci_core_ops - SoC Core Operations
* @reboot_device: Reboot the SoC
* Returns 0 for successful request(ideally should never return),
* else returns corresponding error value.
*/
struct ti_sci_core_ops {
int (*reboot_device)(const struct ti_sci_handle *handle);
};
/**
* struct ti_sci_dev_ops - Device control operations
* @get_device: Command to request for device managed by TISCI
* Returns 0 for successful exclusive request, else returns
* corresponding error message.
* @idle_device: Command to idle a device managed by TISCI
* Returns 0 for successful exclusive request, else returns
* corresponding error message.
* @put_device: Command to release a device managed by TISCI
* Returns 0 for successful release, else returns corresponding
* error message.
* @is_valid: Check if the device ID is a valid ID.
* Returns 0 if the ID is valid, else returns corresponding error.
* @get_context_loss_count: Command to retrieve context loss counter - this
* increments every time the device looses context. Overflow
* is possible.
* - count: pointer to u32 which will retrieve counter
* Returns 0 for successful information request and count has
* proper data, else returns corresponding error message.
* @is_idle: Reports back about device idle state
* - req_state: Returns requested idle state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_stop: Reports back about device stop state
* - req_state: Returns requested stop state
* - current_state: Returns current stop state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_on: Reports back about device ON(or active) state
* - req_state: Returns requested ON state
* - current_state: Returns current ON state
* Returns 0 for successful information request and req_state and
* current_state has proper data, else returns corresponding error
* message.
* @is_transitioning: Reports back if the device is in the middle of transition
* of state.
* -current_state: Returns 'true' if currently transitioning.
* @set_device_resets: Command to configure resets for device managed by TISCI.
* -reset_state: Device specific reset bit field
* Returns 0 for successful request, else returns
* corresponding error message.
* @get_device_resets: Command to read state of resets for device managed
* by TISCI.
* -reset_state: pointer to u32 which will retrieve resets
* Returns 0 for successful request, else returns
* corresponding error message.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* -id: Device Identifier
*
* Request for the device - NOTE: the client MUST maintain integrity of
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
u32 id, u32 *count);
int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
bool *requested_state);
int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
bool *req_state, bool *current_state);
int (*is_on)(const struct ti_sci_handle *handle, u32 id,
bool *req_state, bool *current_state);
int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
bool *current_state);
int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 reset_state);
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 *reset_state);
};
/**
* struct ti_sci_clk_ops - Clock control operations
* @get_clock: Request for activation of clock and manage by processor
* - needs_ssc: 'true' if Spread Spectrum clock is desired.
* - can_change_freq: 'true' if frequency change is desired.
* - enable_input_term: 'true' if input termination is desired.
* @idle_clock: Request for Idling a clock managed by processor
* @put_clock: Release the clock to be auto managed by TISCI
* @is_auto: Is the clock being auto managed
* - req_state: state indicating if the clock is auto managed
* @is_on: Is the clock ON
* - req_state: if the clock is requested to be forced ON
* - current_state: if the clock is currently ON
* @is_off: Is the clock OFF
* - req_state: if the clock is requested to be forced OFF
* - current_state: if the clock is currently Gated
* @set_parent: Set the clock source of a specific device clock
* - parent_id: Parent clock identifier to set.
* @get_parent: Get the current clock source of a specific device clock
* - parent_id: Parent clock identifier which is the parent.
* @get_num_parents: Get the number of parents of the current clock source
* - num_parents: returns the number of parent clocks.
* @get_best_match_freq: Find a best matching frequency for a frequency
* range.
* - match_freq: Best matching frequency in Hz.
* @set_freq: Set the Clock frequency
* @get_freq: Get the Clock frequency
* - current_freq: Frequency in Hz that the clock is at.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* -did: Device identifier this request is for
* -cid: Clock identifier for the device for this request.
* Each device has it's own set of clock inputs. This indexes
* which clock input to modify.
* -min_freq: The minimum allowable frequency in Hz. This is the minimum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
* -target_freq: The target clock frequency in Hz. A frequency will be
* processed as close to this target frequency as possible.
* -max_freq: The maximum allowable frequency in Hz. This is the maximum
* allowable programmed frequency and does not account for clock
* tolerances and jitter.
*
* Request for the clock - NOTE: the client MUST maintain integrity of
* usage count by balancing get_clock with put_clock. No refcounting is
* managed by driver for that purpose.
*/
struct ti_sci_clk_ops {
int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid,
bool needs_ssc, bool can_change_freq,
bool enable_input_term);
int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid,
bool *req_state);
int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid,
bool *req_state, bool *current_state);
int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid,
bool *req_state, bool *current_state);
int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
u8 parent_id);
int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
u8 *parent_id);
int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
u8 cid, u8 *num_parents);
int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
u8 cid, u64 min_freq, u64 target_freq,
u64 max_freq, u64 *match_freq);
int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
u64 min_freq, u64 target_freq, u64 max_freq);
int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
u64 *current_freq);
};
/**
* struct ti_sci_ops - Function support for TI SCI
* @dev_ops: Device specific operations
* @clk_ops: Clock specific operations
*/
struct ti_sci_ops {
struct ti_sci_core_ops core_ops;
struct ti_sci_dev_ops dev_ops;
struct ti_sci_clk_ops clk_ops;
};
/**
* struct ti_sci_handle - Handle returned to TI SCI clients for usage.
* @version: structure containing version information
* @ops: operations that are made available to TI SCI clients
*/
struct ti_sci_handle {
struct ti_sci_version_info version;
struct ti_sci_ops ops;
};
#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
int ti_sci_put_handle(const struct ti_sci_handle *handle);
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
#else /* CONFIG_TI_SCI_PROTOCOL */
static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
{
return ERR_PTR(-EINVAL);
}
static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
{
return -EINVAL;
}
static inline
const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
{
return ERR_PTR(-EINVAL);
}
#endif /* CONFIG_TI_SCI_PROTOCOL */
#endif /* __TISCI_PROTOCOL_H */

19
include/soc/at91/atmel-secumod.h Normal file
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@ -0,0 +1,19 @@
/*
* Atmel Security Module register offsets and bit definitions.
*
* Copyright (C) 2016 Atmel
*
* Author: Alexandre Belloni <alexandre.belloni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _LINUX_SOC_AT91_ATMEL_SECUMOD_H
#define _LINUX_SOC_AT91_ATMEL_SECUMOD_H
#define AT91_SECUMOD_RAMRDY 0x14
#define AT91_SECUMOD_RAMRDY_READY BIT(0)
#endif /* _LINUX_SOC_AT91_ATMEL_SECUMOD_H */

1601
include/soc/tegra/bpmp-abi.h Normal file
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File diff suppressed because it is too large Load Diff

141
include/soc/tegra/bpmp.h Normal file
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@ -0,0 +1,141 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __SOC_TEGRA_BPMP_H
#define __SOC_TEGRA_BPMP_H
#include <linux/mailbox_client.h>
#include <linux/reset-controller.h>
#include <linux/semaphore.h>
#include <linux/types.h>
#include <soc/tegra/bpmp-abi.h>
struct tegra_bpmp_clk;
struct tegra_bpmp_soc {
struct {
struct {
unsigned int offset;
unsigned int count;
unsigned int timeout;
} cpu_tx, thread, cpu_rx;
} channels;
unsigned int num_resets;
};
struct tegra_bpmp_mb_data {
u32 code;
u32 flags;
u8 data[MSG_DATA_MIN_SZ];
} __packed;
struct tegra_bpmp_channel {
struct tegra_bpmp *bpmp;
struct tegra_bpmp_mb_data *ib;
struct tegra_bpmp_mb_data *ob;
struct completion completion;
struct tegra_ivc *ivc;
};
typedef void (*tegra_bpmp_mrq_handler_t)(unsigned int mrq,
struct tegra_bpmp_channel *channel,
void *data);
struct tegra_bpmp_mrq {
struct list_head list;
unsigned int mrq;
tegra_bpmp_mrq_handler_t handler;
void *data;
};
struct tegra_bpmp {
const struct tegra_bpmp_soc *soc;
struct device *dev;
struct {
struct gen_pool *pool;
dma_addr_t phys;
void *virt;
} tx, rx;
struct {
struct mbox_client client;
struct mbox_chan *channel;
} mbox;
struct tegra_bpmp_channel *channels;
unsigned int num_channels;
struct {
unsigned long *allocated;
unsigned long *busy;
unsigned int count;
struct semaphore lock;
} threaded;
struct list_head mrqs;
spinlock_t lock;
struct tegra_bpmp_clk **clocks;
unsigned int num_clocks;
struct reset_controller_dev rstc;
};
struct tegra_bpmp *tegra_bpmp_get(struct device *dev);
void tegra_bpmp_put(struct tegra_bpmp *bpmp);
struct tegra_bpmp_message {
unsigned int mrq;
struct {
const void *data;
size_t size;
} tx;
struct {
void *data;
size_t size;
} rx;
};
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg);
int tegra_bpmp_transfer(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg);
int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq,
tegra_bpmp_mrq_handler_t handler, void *data);
void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq,
void *data);
#if IS_ENABLED(CONFIG_CLK_TEGRA_BPMP)
int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_RESET_TEGRA_BPMP)
int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp);
#else
static inline int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp)
{
return 0;
}
#endif
#endif /* __SOC_TEGRA_BPMP_H */

109
include/soc/tegra/ivc.h Normal file
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@ -0,0 +1,109 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __TEGRA_IVC_H
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/types.h>
struct tegra_ivc_header;
struct tegra_ivc {
struct device *peer;
struct {
struct tegra_ivc_header *channel;
unsigned int position;
dma_addr_t phys;
} rx, tx;
void (*notify)(struct tegra_ivc *ivc, void *data);
void *notify_data;
unsigned int num_frames;
size_t frame_size;
};
/**
* tegra_ivc_read_get_next_frame - Peek at the next frame to receive
* @ivc pointer of the IVC channel
*
* Peek at the next frame to be received, without removing it from
* the queue.
*
* Returns a pointer to the frame, or an error encoded pointer.
*/
void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc);
/**
* tegra_ivc_read_advance - Advance the read queue
* @ivc pointer of the IVC channel
*
* Advance the read queue
*
* Returns 0, or a negative error value if failed.
*/
int tegra_ivc_read_advance(struct tegra_ivc *ivc);
/**
* tegra_ivc_write_get_next_frame - Poke at the next frame to transmit
* @ivc pointer of the IVC channel
*
* Get access to the next frame.
*
* Returns a pointer to the frame, or an error encoded pointer.
*/
void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc);
/**
* tegra_ivc_write_advance - Advance the write queue
* @ivc pointer of the IVC channel
*
* Advance the write queue
*
* Returns 0, or a negative error value if failed.
*/
int tegra_ivc_write_advance(struct tegra_ivc *ivc);
/**
* tegra_ivc_notified - handle internal messages
* @ivc pointer of the IVC channel
*
* This function must be called following every notification.
*
* Returns 0 if the channel is ready for communication, or -EAGAIN if a channel
* reset is in progress.
*/
int tegra_ivc_notified(struct tegra_ivc *ivc);
/**
* tegra_ivc_reset - initiates a reset of the shared memory state
* @ivc pointer of the IVC channel
*
* This function must be called after a channel is reserved before it is used
* for communication. The channel will be ready for use when a subsequent call
* to notify the remote of the channel reset.
*/
void tegra_ivc_reset(struct tegra_ivc *ivc);
size_t tegra_ivc_align(size_t size);
unsigned tegra_ivc_total_queue_size(unsigned queue_size);
int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx,
dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys,
unsigned int num_frames, size_t frame_size,
void (*notify)(struct tegra_ivc *ivc, void *data),
void *data);
void tegra_ivc_cleanup(struct tegra_ivc *ivc);
#endif /* __TEGRA_IVC_H */

126
include/soc/tegra/pmc.h
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@ -76,37 +76,73 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
#define TEGRA_IO_RAIL_CSIA 0
#define TEGRA_IO_RAIL_CSIB 1
#define TEGRA_IO_RAIL_DSI 2
#define TEGRA_IO_RAIL_MIPI_BIAS 3
#define TEGRA_IO_RAIL_PEX_BIAS 4
#define TEGRA_IO_RAIL_PEX_CLK1 5
#define TEGRA_IO_RAIL_PEX_CLK2 6
#define TEGRA_IO_RAIL_USB0 9
#define TEGRA_IO_RAIL_USB1 10
#define TEGRA_IO_RAIL_USB2 11
#define TEGRA_IO_RAIL_USB_BIAS 12
#define TEGRA_IO_RAIL_NAND 13
#define TEGRA_IO_RAIL_UART 14
#define TEGRA_IO_RAIL_BB 15
#define TEGRA_IO_RAIL_AUDIO 17
#define TEGRA_IO_RAIL_HSIC 19
#define TEGRA_IO_RAIL_COMP 22
#define TEGRA_IO_RAIL_HDMI 28
#define TEGRA_IO_RAIL_PEX_CNTRL 32
#define TEGRA_IO_RAIL_SDMMC1 33
#define TEGRA_IO_RAIL_SDMMC3 34
#define TEGRA_IO_RAIL_SDMMC4 35
#define TEGRA_IO_RAIL_CAM 36
#define TEGRA_IO_RAIL_RES 37
#define TEGRA_IO_RAIL_HV 38
#define TEGRA_IO_RAIL_DSIB 39
#define TEGRA_IO_RAIL_DSIC 40
#define TEGRA_IO_RAIL_DSID 41
#define TEGRA_IO_RAIL_CSIE 44
#define TEGRA_IO_RAIL_LVDS 57
#define TEGRA_IO_RAIL_SYS_DDC 58
/**
* enum tegra_io_pad - I/O pad group identifier
*
* I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
* can be used to control the common voltage signal level and power state of
* the pins of the given pad.
*/
enum tegra_io_pad {
TEGRA_IO_PAD_AUDIO,
TEGRA_IO_PAD_AUDIO_HV,
TEGRA_IO_PAD_BB,
TEGRA_IO_PAD_CAM,
TEGRA_IO_PAD_COMP,
TEGRA_IO_PAD_CSIA,
TEGRA_IO_PAD_CSIB,
TEGRA_IO_PAD_CSIC,
TEGRA_IO_PAD_CSID,
TEGRA_IO_PAD_CSIE,
TEGRA_IO_PAD_CSIF,
TEGRA_IO_PAD_DBG,
TEGRA_IO_PAD_DEBUG_NONAO,
TEGRA_IO_PAD_DMIC,
TEGRA_IO_PAD_DP,
TEGRA_IO_PAD_DSI,
TEGRA_IO_PAD_DSIB,
TEGRA_IO_PAD_DSIC,
TEGRA_IO_PAD_DSID,
TEGRA_IO_PAD_EMMC,
TEGRA_IO_PAD_EMMC2,
TEGRA_IO_PAD_GPIO,
TEGRA_IO_PAD_HDMI,
TEGRA_IO_PAD_HSIC,
TEGRA_IO_PAD_HV,
TEGRA_IO_PAD_LVDS,
TEGRA_IO_PAD_MIPI_BIAS,
TEGRA_IO_PAD_NAND,
TEGRA_IO_PAD_PEX_BIAS,
TEGRA_IO_PAD_PEX_CLK1,
TEGRA_IO_PAD_PEX_CLK2,
TEGRA_IO_PAD_PEX_CNTRL,
TEGRA_IO_PAD_SDMMC1,
TEGRA_IO_PAD_SDMMC3,
TEGRA_IO_PAD_SDMMC4,
TEGRA_IO_PAD_SPI,
TEGRA_IO_PAD_SPI_HV,
TEGRA_IO_PAD_SYS_DDC,
TEGRA_IO_PAD_UART,
TEGRA_IO_PAD_USB0,
TEGRA_IO_PAD_USB1,
TEGRA_IO_PAD_USB2,
TEGRA_IO_PAD_USB3,
TEGRA_IO_PAD_USB_BIAS,
};
/* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
#define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
#define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
/**
* enum tegra_io_pad_voltage - voltage level of the I/O pad's source rail
* @TEGRA_IO_PAD_1800000UV: 1.8 V
* @TEGRA_IO_PAD_3300000UV: 3.3 V
*/
enum tegra_io_pad_voltage {
TEGRA_IO_PAD_1800000UV,
TEGRA_IO_PAD_3300000UV,
};
#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(unsigned int id);
@ -118,6 +154,13 @@ int tegra_powergate_remove_clamping(unsigned int id);
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
struct reset_control *rst);
int tegra_io_pad_power_enable(enum tegra_io_pad id);
int tegra_io_pad_power_disable(enum tegra_io_pad id);
int tegra_io_pad_set_voltage(enum tegra_io_pad id,
enum tegra_io_pad_voltage voltage);
int tegra_io_pad_get_voltage(enum tegra_io_pad id);
/* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
int tegra_io_rail_power_on(unsigned int id);
int tegra_io_rail_power_off(unsigned int id);
#else
@ -148,6 +191,27 @@ static inline int tegra_powergate_sequence_power_up(unsigned int id,
return -ENOSYS;
}
static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
{
return -ENOSYS;
}
static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
{
return -ENOSYS;
}
static inline int tegra_io_pad_set_voltage(enum tegra_io_pad id,
enum tegra_io_pad_voltage voltage)
{
return -ENOSYS;
}
static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
{
return -ENOSYS;
}
static inline int tegra_io_rail_power_on(unsigned int id)
{
return -ENOSYS;