Staging: olpc_dcon: replace some magic numbers
This patch replace some magic numbers. I believe it makes the driver more readable. The magic number 0x26 is the XO system embedded controller (EC) command 'DCON power enable/disable'. Number 0x41, and 0x42 are special memory controller settings register. The 0x41 initialize bit sequence 0x101 means: enable memory power down function and special SDRAM clock delay for synchronize SDRAM output and clock signal. The 0x42 initialize squence 0x101 is wrong. According to the specification Bit 8 is reserved, thus not in use. I removed it. Signed-off-by: Jens Frederich <jfrederich@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -90,9 +90,10 @@ static int dcon_hw_init(struct dcon_priv *dcon, int is_init)
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/* SDRAM setup/hold time */
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dcon_write(dcon, 0x3a, 0xc040);
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dcon_write(dcon, 0x41, 0x0000);
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dcon_write(dcon, 0x41, 0x0101);
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dcon_write(dcon, 0x42, 0x0101);
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dcon_write(dcon, DCON_REG_MEM_OPT_A, 0x0000); /* clear option bits */
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dcon_write(dcon, DCON_REG_MEM_OPT_A,
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MEM_DLL_CLOCK_DELAY | MEM_POWER_DOWN);
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dcon_write(dcon, DCON_REG_MEM_OPT_B, MEM_SOFT_RESET);
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/* Colour swizzle, AA, no passthrough, backlight */
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if (is_init) {
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@ -126,7 +127,7 @@ static int dcon_bus_stabilize(struct dcon_priv *dcon, int is_powered_down)
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power_up:
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if (is_powered_down) {
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x = 1;
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x = olpc_ec_cmd(0x26, (unsigned char *)&x, 1, NULL, 0);
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x = olpc_ec_cmd(EC_DCON_POWER_MODE, (u8 *)&x, 1, NULL, 0);
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if (x) {
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pr_warn("unable to force dcon to power up: %d!\n", x);
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return x;
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@ -144,7 +145,7 @@ power_up:
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pr_err("unable to stabilize dcon's smbus, reasserting power and praying.\n");
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BUG_ON(olpc_board_at_least(olpc_board(0xc2)));
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x = 0;
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olpc_ec_cmd(0x26, (unsigned char *)&x, 1, NULL, 0);
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olpc_ec_cmd(EC_DCON_POWER_MODE, (u8 *)&x, 1, NULL, 0);
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msleep(100);
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is_powered_down = 1;
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goto power_up; /* argh, stupid hardware.. */
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@ -208,7 +209,7 @@ static void dcon_sleep(struct dcon_priv *dcon, bool sleep)
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if (sleep) {
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x = 0;
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x = olpc_ec_cmd(0x26, (unsigned char *)&x, 1, NULL, 0);
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x = olpc_ec_cmd(EC_DCON_POWER_MODE, (u8 *)&x, 1, NULL, 0);
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if (x)
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pr_warn("unable to force dcon to power down: %d!\n", x);
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else
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@ -22,15 +22,24 @@
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#define MODE_DEBUG (1<<14)
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#define MODE_SELFTEST (1<<15)
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#define DCON_REG_HRES 2
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#define DCON_REG_HTOTAL 3
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#define DCON_REG_HSYNC_WIDTH 4
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#define DCON_REG_VRES 5
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#define DCON_REG_VTOTAL 6
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#define DCON_REG_VSYNC_WIDTH 7
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#define DCON_REG_TIMEOUT 8
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#define DCON_REG_SCAN_INT 9
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#define DCON_REG_BRIGHT 10
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#define DCON_REG_HRES 0x2
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#define DCON_REG_HTOTAL 0x3
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#define DCON_REG_HSYNC_WIDTH 0x4
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#define DCON_REG_VRES 0x5
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#define DCON_REG_VTOTAL 0x6
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#define DCON_REG_VSYNC_WIDTH 0x7
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#define DCON_REG_TIMEOUT 0x8
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#define DCON_REG_SCAN_INT 0x9
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#define DCON_REG_BRIGHT 0x10
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#define DCON_REG_MEM_OPT_A 0x41
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#define DCON_REG_MEM_OPT_B 0x42
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/* Load Delay Locked Loop (DLL) settings for clock delay */
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#define MEM_DLL_CLOCK_DELAY (1<<0)
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/* Memory controller power down function */
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#define MEM_POWER_DOWN (1<<8)
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/* Memory controller software reset */
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#define MEM_SOFT_RESET (1<<0)
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/* Status values */
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@ -6,6 +6,7 @@
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#define EC_WRITE_SCI_MASK 0x1b
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#define EC_WAKE_UP_WLAN 0x24
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#define EC_WLAN_LEAVE_RESET 0x25
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#define EC_DCON_POWER_MODE 0x26
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#define EC_READ_EB_MODE 0x2a
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#define EC_SET_SCI_INHIBIT 0x32
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#define EC_SET_SCI_INHIBIT_RELEASE 0x34
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