Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (38 commits) amd64_edac: Fix decode_syndrome types amd64_edac: Fix DCT argument type amd64_edac: Fix ranges signedness amd64_edac: Drop local variable amd64_edac: Fix PCI config addressing types amd64_edac: Fix DRAM base macros amd64_edac: Fix node id signedness amd64_edac: Drop redundant declarations amd64_edac: Enable driver on F15h amd64_edac: Adjust ECC symbol size to F15h amd64_edac: Simplify scrubrate setting PCI: Rename CPU PCI id define amd64_edac: Improve DRAM address mapping amd64_edac: Sanitize ->read_dram_ctl_register amd64_edac: Adjust sys_addr to chip select conversion routine to F15h amd64_edac: Beef up early exit reporting amd64_edac: Revamp online spare handling amd64_edac: Fix channel interleave removal amd64_edac: Correct node interleaving removal amd64_edac: Add support for interleaved region swapping ... Fix up trivial conflict in include/linux/pci_ids.h due to AMD_15H_NB_MISC being renamed as AMD_15H_NB_F3 next to the new AMD_15H_NB_LINK entry.
This commit is contained in:
Linus Torvalds
commit
978ca164bd
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@ -15,7 +15,7 @@ static u32 *flush_words;
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const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{}
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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File diff suppressed because it is too large
Load Diff
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@ -144,7 +144,7 @@
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* sections 3.5.4 and 3.5.5 for more information.
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*/
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#define EDAC_AMD64_VERSION "v3.3.0"
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#define EDAC_AMD64_VERSION "3.4.0"
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#define EDAC_MOD_STR "amd64_edac"
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/* Extended Model from CPUID, for CPU Revision numbers */
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@ -153,85 +153,64 @@
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#define K8_REV_F 4
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/* Hardware limit on ChipSelect rows per MC and processors per system */
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#define MAX_CS_COUNT 8
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#define DRAM_REG_COUNT 8
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#define NUM_CHIPSELECTS 8
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#define DRAM_RANGES 8
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#define ON true
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#define OFF false
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/*
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* Create a contiguous bitmask starting at bit position @lo and ending at
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* position @hi. For example
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*
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* GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
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*/
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#define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
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/*
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* PCI-defined configuration space registers
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*/
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#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
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#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
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/*
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* Function 1 - Address Map
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*/
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#define K8_DRAM_BASE_LOW 0x40
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#define K8_DRAM_LIMIT_LOW 0x44
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#define K8_DHAR 0xf0
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#define DRAM_BASE_LO 0x40
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#define DRAM_LIMIT_LO 0x44
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#define DHAR_VALID BIT(0)
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#define F10_DRAM_MEM_HOIST_VALID BIT(1)
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#define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
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#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
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#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
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#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
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#define DHAR_BASE_MASK 0xff000000
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#define dhar_base(dhar) (dhar & DHAR_BASE_MASK)
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#define DHAR 0xf0
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#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
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#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
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#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
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#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
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#define K8_DHAR_OFFSET_MASK 0x0000ff00
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#define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16)
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#define F10_DHAR_OFFSET_MASK 0x0000ff80
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/* NOTE: Extra mask bit vs K8 */
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#define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
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#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
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#define DCT_CFG_SEL 0x10C
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/* F10 High BASE/LIMIT registers */
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#define F10_DRAM_BASE_HIGH 0x140
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#define F10_DRAM_LIMIT_HIGH 0x144
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#define DRAM_BASE_HI 0x140
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#define DRAM_LIMIT_HI 0x144
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/*
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* Function 2 - DRAM controller
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*/
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#define K8_DCSB0 0x40
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#define F10_DCSB1 0x140
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#define DCSB0 0x40
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#define DCSB1 0x140
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#define DCSB_CS_ENABLE BIT(0)
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#define K8_DCSB_CS_ENABLE BIT(0)
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#define K8_DCSB_NPT_SPARE BIT(1)
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#define K8_DCSB_NPT_TESTFAIL BIT(2)
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#define DCSM0 0x60
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#define DCSM1 0x160
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/*
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* REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
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* the address
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*/
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#define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
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#define REV_E_DCS_SHIFT 4
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#define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL)
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#define REV_F_F1Xh_DCS_SHIFT 8
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/*
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* REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
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* to form the address
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*/
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#define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
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#define REV_F_DCS_SHIFT 8
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/* DRAM CS Mask Registers */
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#define K8_DCSM0 0x60
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#define F10_DCSM1 0x160
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/* REV E: select [29:21] and [15:9] from DCSM */
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#define REV_E_DCSM_MASK_BITS 0x3FE0FE00
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/* unused bits [24:20] and [12:0] */
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#define REV_E_DCS_NOTUSED_BITS 0x01F01FFF
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/* REV F and later: select [28:19] and [13:5] from DCSM */
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#define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0
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/* unused bits [26:22] and [12:0] */
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#define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF
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#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
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#define DBAM0 0x80
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#define DBAM1 0x180
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@ -241,148 +220,84 @@
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#define DBAM_MAX_VALUE 11
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#define F10_DCLR_0 0x90
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#define F10_DCLR_1 0x190
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#define DCLR0 0x90
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#define DCLR1 0x190
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#define REVE_WIDTH_128 BIT(16)
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#define F10_WIDTH_128 BIT(11)
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#define WIDTH_128 BIT(11)
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#define F10_DCHR_0 0x94
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#define F10_DCHR_1 0x194
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#define F10_DCHR_FOUR_RANK_DIMM BIT(18)
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#define DCHR0 0x94
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#define DCHR1 0x194
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#define DDR3_MODE BIT(8)
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#define F10_DCHR_MblMode BIT(6)
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#define DCT_SEL_LO 0x110
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#define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
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#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
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#define F10_DCTL_SEL_LOW 0x110
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#define dct_sel_baseaddr(pvt) ((pvt->dram_ctl_select_low) & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt->dram_ctl_select_low) >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) (pvt->dram_ctl_select_low & BIT(0))
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#define dct_interleave_enabled(pvt) (pvt->dram_ctl_select_low & BIT(2))
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#define dct_ganging_enabled(pvt) (pvt->dram_ctl_select_low & BIT(4))
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#define dct_data_intlv_enabled(pvt) (pvt->dram_ctl_select_low & BIT(5))
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#define dct_dram_enabled(pvt) (pvt->dram_ctl_select_low & BIT(8))
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#define dct_memory_cleared(pvt) (pvt->dram_ctl_select_low & BIT(10))
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
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#define F10_DCTL_SEL_HIGH 0x114
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#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
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#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
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#define SWAP_INTLV_REG 0x10c
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#define DCT_SEL_HI 0x114
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/*
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* Function 3 - Misc Control
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*/
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#define K8_NBCTL 0x40
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#define NBCTL 0x40
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/* Correctable ECC error reporting enable */
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#define K8_NBCTL_CECCEn BIT(0)
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#define NBCFG 0x44
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#define NBCFG_CHIPKILL BIT(23)
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#define NBCFG_ECC_ENABLE BIT(22)
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/* UnCorrectable ECC error reporting enable */
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#define K8_NBCTL_UECCEn BIT(1)
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#define K8_NBCFG 0x44
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#define K8_NBCFG_CHIPKILL BIT(23)
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#define K8_NBCFG_ECC_ENABLE BIT(22)
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#define K8_NBSL 0x48
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/* Family F10h: Normalized Extended Error Codes */
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#define F10_NBSL_EXT_ERR_RES 0x0
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/* F3x48: NBSL */
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#define F10_NBSL_EXT_ERR_ECC 0x8
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#define NBSL_PP_OBS 0x2
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/* Next two are overloaded values */
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#define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
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#define F10_NBSL_EXT_ERR_L3_PROTO 0xB
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#define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
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#define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
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#define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
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/* Next two are overloaded values */
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#define F10_NBSL_EXT_ERR_GART_WALK 0xF
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#define F10_NBSL_EXT_ERR_DEV_WALK 0xF
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/* 0x10 to 0x1B: Reserved */
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#define F10_NBSL_EXT_ERR_L3_DATA 0x1C
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#define F10_NBSL_EXT_ERR_L3_TAG 0x1D
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#define F10_NBSL_EXT_ERR_L3_LRU 0x1E
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/* K8: Normalized Extended Error Codes */
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#define K8_NBSL_EXT_ERR_ECC 0x0
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#define K8_NBSL_EXT_ERR_CRC 0x1
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#define K8_NBSL_EXT_ERR_SYNC 0x2
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#define K8_NBSL_EXT_ERR_MST 0x3
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#define K8_NBSL_EXT_ERR_TGT 0x4
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#define K8_NBSL_EXT_ERR_GART 0x5
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#define K8_NBSL_EXT_ERR_RMW 0x6
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#define K8_NBSL_EXT_ERR_WDT 0x7
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#define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
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#define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
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/*
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* The following are for BUS type errors AFTER values have been normalized by
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* shifting right
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*/
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#define K8_NBSL_PP_SRC 0x0
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#define K8_NBSL_PP_RES 0x1
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#define K8_NBSL_PP_OBS 0x2
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#define K8_NBSL_PP_GENERIC 0x3
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#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
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#define K8_NBEAL 0x50
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#define K8_NBEAH 0x54
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#define K8_SCRCTRL 0x58
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#define F10_NB_CFG_LOW 0x88
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#define SCRCTRL 0x58
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#define F10_ONLINE_SPARE 0xB0
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#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
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#define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
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#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
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#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
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#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
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#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
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#define F10_NB_ARRAY_ADDR 0xB8
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#define F10_NB_ARRAY_DRAM_ECC 0x80000000
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#define F10_NB_ARRAY_DRAM_ECC BIT(31)
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|
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/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
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#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
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|
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#define F10_NB_ARRAY_DATA 0xBC
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|
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#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
|
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(BIT(((word) & 0xF) + 20) | \
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BIT(17) | bits)
|
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|
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#define SET_NB_DRAM_INJECTION_READ(word, bits) \
|
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(BIT(((word) & 0xF) + 20) | \
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BIT(16) | bits)
|
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|
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#define K8_NBCAP 0xE8
|
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#define K8_NBCAP_CORES (BIT(12)|BIT(13))
|
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#define K8_NBCAP_CHIPKILL BIT(4)
|
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#define K8_NBCAP_SECDED BIT(3)
|
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#define K8_NBCAP_DCT_DUAL BIT(0)
|
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#define NBCAP 0xE8
|
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#define NBCAP_CHIPKILL BIT(4)
|
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#define NBCAP_SECDED BIT(3)
|
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#define NBCAP_DCT_DUAL BIT(0)
|
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|
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#define EXT_NB_MCA_CFG 0x180
|
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|
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/* MSRs */
|
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#define K8_MSR_MCGCTL_NBE BIT(4)
|
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|
||||
#define K8_MSR_MC4CTL 0x0410
|
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#define K8_MSR_MC4STAT 0x0411
|
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#define K8_MSR_MC4ADDR 0x0412
|
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#define MSR_MCGCTL_NBE BIT(4)
|
||||
|
||||
/* AMD sets the first MC device at device ID 0x18. */
|
||||
static inline int get_node_id(struct pci_dev *pdev)
|
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static inline u8 get_node_id(struct pci_dev *pdev)
|
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{
|
||||
return PCI_SLOT(pdev->devfn) - 0x18;
|
||||
}
|
||||
|
||||
enum amd64_chipset_families {
|
||||
enum amd_families {
|
||||
K8_CPUS = 0,
|
||||
F10_CPUS,
|
||||
F15_CPUS,
|
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NUM_FAMILIES,
|
||||
};
|
||||
|
||||
/* Error injection control structure */
|
||||
|
|
@ -392,13 +307,35 @@ struct error_injection {
|
|||
u32 bit_map;
|
||||
};
|
||||
|
||||
/* low and high part of PCI config space regs */
|
||||
struct reg_pair {
|
||||
u32 lo, hi;
|
||||
};
|
||||
|
||||
/*
|
||||
* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
|
||||
*/
|
||||
struct dram_range {
|
||||
struct reg_pair base;
|
||||
struct reg_pair lim;
|
||||
};
|
||||
|
||||
/* A DCT chip selects collection */
|
||||
struct chip_select {
|
||||
u32 csbases[NUM_CHIPSELECTS];
|
||||
u8 b_cnt;
|
||||
|
||||
u32 csmasks[NUM_CHIPSELECTS];
|
||||
u8 m_cnt;
|
||||
};
|
||||
|
||||
struct amd64_pvt {
|
||||
struct low_ops *ops;
|
||||
|
||||
/* pci_device handles which we utilize */
|
||||
struct pci_dev *F1, *F2, *F3;
|
||||
|
||||
int mc_node_id; /* MC index of this MC node */
|
||||
unsigned mc_node_id; /* MC index of this MC node */
|
||||
int ext_model; /* extended model value of this node */
|
||||
int channel_count;
|
||||
|
||||
|
|
@ -414,61 +351,51 @@ struct amd64_pvt {
|
|||
u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
|
||||
u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
|
||||
|
||||
/* DRAM CS Base Address Registers F2x[1,0][5C:40] */
|
||||
u32 dcsb0[MAX_CS_COUNT];
|
||||
u32 dcsb1[MAX_CS_COUNT];
|
||||
/* one for each DCT */
|
||||
struct chip_select csels[2];
|
||||
|
||||
/* DRAM CS Mask Registers F2x[1,0][6C:60] */
|
||||
u32 dcsm0[MAX_CS_COUNT];
|
||||
u32 dcsm1[MAX_CS_COUNT];
|
||||
|
||||
/*
|
||||
* Decoded parts of DRAM BASE and LIMIT Registers
|
||||
* F1x[78,70,68,60,58,50,48,40]
|
||||
*/
|
||||
u64 dram_base[DRAM_REG_COUNT];
|
||||
u64 dram_limit[DRAM_REG_COUNT];
|
||||
u8 dram_IntlvSel[DRAM_REG_COUNT];
|
||||
u8 dram_IntlvEn[DRAM_REG_COUNT];
|
||||
u8 dram_DstNode[DRAM_REG_COUNT];
|
||||
u8 dram_rw_en[DRAM_REG_COUNT];
|
||||
|
||||
/*
|
||||
* The following fields are set at (load) run time, after CPU revision
|
||||
* has been determined, since the dct_base and dct_mask registers vary
|
||||
* based on revision
|
||||
*/
|
||||
u32 dcsb_base; /* DCSB base bits */
|
||||
u32 dcsm_mask; /* DCSM mask bits */
|
||||
u32 cs_count; /* num chip selects (== num DCSB registers) */
|
||||
u32 num_dcsm; /* Number of DCSM registers */
|
||||
u32 dcs_mask_notused; /* DCSM notused mask bits */
|
||||
u32 dcs_shift; /* DCSB and DCSM shift value */
|
||||
/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
|
||||
struct dram_range ranges[DRAM_RANGES];
|
||||
|
||||
u64 top_mem; /* top of memory below 4GB */
|
||||
u64 top_mem2; /* top of memory above 4GB */
|
||||
|
||||
u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */
|
||||
u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
|
||||
u32 online_spare; /* On-Line spare Reg */
|
||||
u32 dct_sel_lo; /* DRAM Controller Select Low */
|
||||
u32 dct_sel_hi; /* DRAM Controller Select High */
|
||||
u32 online_spare; /* On-Line spare Reg */
|
||||
|
||||
/* x4 or x8 syndromes in use */
|
||||
u8 syn_type;
|
||||
|
||||
/* temp storage for when input is received from sysfs */
|
||||
struct err_regs ctl_error_info;
|
||||
u8 ecc_sym_sz;
|
||||
|
||||
/* place to store error injection parameters prior to issue */
|
||||
struct error_injection injection;
|
||||
|
||||
/* DCT per-family scrubrate setting */
|
||||
u32 min_scrubrate;
|
||||
|
||||
/* family name this instance is running on */
|
||||
const char *ctl_name;
|
||||
|
||||
};
|
||||
|
||||
static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
|
||||
{
|
||||
u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
|
||||
|
||||
if (boot_cpu_data.x86 == 0xf)
|
||||
return addr;
|
||||
|
||||
return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
|
||||
}
|
||||
|
||||
static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
|
||||
{
|
||||
u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
|
||||
|
||||
if (boot_cpu_data.x86 == 0xf)
|
||||
return lim;
|
||||
|
||||
return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
|
||||
}
|
||||
|
||||
static inline u16 extract_syndrome(u64 status)
|
||||
{
|
||||
return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
|
||||
}
|
||||
|
||||
/*
|
||||
* per-node ECC settings descriptor
|
||||
*/
|
||||
|
|
@ -482,14 +409,6 @@ struct ecc_settings {
|
|||
} flags;
|
||||
};
|
||||
|
||||
extern const char *tt_msgs[4];
|
||||
extern const char *ll_msgs[4];
|
||||
extern const char *rrrr_msgs[16];
|
||||
extern const char *to_msgs[2];
|
||||
extern const char *pp_msgs[4];
|
||||
extern const char *ii_msgs[4];
|
||||
extern const char *htlink_msgs[8];
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
#define NUM_DBG_ATTRS 5
|
||||
#else
|
||||
|
|
@ -511,14 +430,11 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
|
|||
*/
|
||||
struct low_ops {
|
||||
int (*early_channel_count) (struct amd64_pvt *pvt);
|
||||
|
||||
u64 (*get_error_address) (struct mem_ctl_info *mci,
|
||||
struct err_regs *info);
|
||||
void (*read_dram_base_limit) (struct amd64_pvt *pvt, int dram);
|
||||
void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
|
||||
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
|
||||
struct err_regs *info, u64 SystemAddr);
|
||||
int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
|
||||
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
|
||||
u16 syndrome);
|
||||
int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
|
||||
int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
|
||||
u32 *val, const char *func);
|
||||
};
|
||||
|
||||
struct amd64_family_type {
|
||||
|
|
@ -527,28 +443,17 @@ struct amd64_family_type {
|
|||
struct low_ops ops;
|
||||
};
|
||||
|
||||
static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
|
||||
u32 *val, const char *func)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
err = pci_read_config_dword(pdev, offset, val);
|
||||
if (err)
|
||||
amd64_warn("%s: error reading F%dx%x.\n",
|
||||
func, PCI_FUNC(pdev->devfn), offset);
|
||||
|
||||
return err;
|
||||
}
|
||||
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
|
||||
u32 val, const char *func);
|
||||
|
||||
#define amd64_read_pci_cfg(pdev, offset, val) \
|
||||
amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
|
||||
/*
|
||||
* For future CPU versions, verify the following as new 'slow' rates appear and
|
||||
* modify the necessary skip values for the supported CPU.
|
||||
*/
|
||||
#define K8_MIN_SCRUB_RATE_BITS 0x0
|
||||
#define F10_MIN_SCRUB_RATE_BITS 0x5
|
||||
#define amd64_write_pci_cfg(pdev, offset, val) \
|
||||
__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
|
||||
#define amd64_read_dct_pci_cfg(pvt, offset, val) \
|
||||
pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
|
||||
|
||||
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
|
||||
u64 *hole_offset, u64 *hole_size);
|
||||
|
|
|
|||
|
|
@ -117,13 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
|
|||
/* Form value to choose 16-byte section of cacheline */
|
||||
section = F10_NB_ARRAY_DRAM_ECC |
|
||||
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
|
||||
word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
|
||||
pvt->injection.bit_map);
|
||||
|
||||
/* Issue 'word' and 'bit' along with the READ request */
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
|
||||
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
|
||||
|
||||
|
|
@ -150,13 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
|
|||
/* Form value to choose 16-byte section of cacheline */
|
||||
section = F10_NB_ARRAY_DRAM_ECC |
|
||||
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
|
||||
word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
|
||||
pvt->injection.bit_map);
|
||||
|
||||
/* Issue 'word' and 'bit' along with the READ request */
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
|
||||
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
|
||||
|
||||
|
|
|
|||
|
|
@ -785,10 +785,10 @@ static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
|
|||
{
|
||||
int err;
|
||||
|
||||
debugf1("%s()\n", __func__);
|
||||
debugf4("%s()\n", __func__);
|
||||
|
||||
while (sysfs_attrib) {
|
||||
debugf1("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
|
||||
debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
|
||||
if (sysfs_attrib->grp) {
|
||||
struct mcidev_sysfs_group_kobj *grp_kobj;
|
||||
|
||||
|
|
@ -818,7 +818,7 @@ static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
|
|||
if (err < 0)
|
||||
return err;
|
||||
} else if (sysfs_attrib->attr.name) {
|
||||
debugf0("%s() file %s\n", __func__,
|
||||
debugf4("%s() file %s\n", __func__,
|
||||
sysfs_attrib->attr.name);
|
||||
|
||||
err = sysfs_create_file(kobj, &sysfs_attrib->attr);
|
||||
|
|
@ -853,26 +853,26 @@ static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
|
|||
* Remove first all the atributes
|
||||
*/
|
||||
while (sysfs_attrib) {
|
||||
debugf1("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
|
||||
debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
|
||||
if (sysfs_attrib->grp) {
|
||||
debugf1("%s() seeking for group %s\n",
|
||||
debugf4("%s() seeking for group %s\n",
|
||||
__func__, sysfs_attrib->grp->name);
|
||||
list_for_each_entry(grp_kobj,
|
||||
&mci->grp_kobj_list, list) {
|
||||
debugf1("%s() grp_kobj->grp = %p\n",__func__, grp_kobj->grp);
|
||||
debugf4("%s() grp_kobj->grp = %p\n",__func__, grp_kobj->grp);
|
||||
if (grp_kobj->grp == sysfs_attrib->grp) {
|
||||
edac_remove_mci_instance_attributes(mci,
|
||||
grp_kobj->grp->mcidev_attr,
|
||||
&grp_kobj->kobj, count + 1);
|
||||
debugf0("%s() group %s\n", __func__,
|
||||
debugf4("%s() group %s\n", __func__,
|
||||
sysfs_attrib->grp->name);
|
||||
kobject_put(&grp_kobj->kobj);
|
||||
}
|
||||
}
|
||||
debugf1("%s() end of seeking for group %s\n",
|
||||
debugf4("%s() end of seeking for group %s\n",
|
||||
__func__, sysfs_attrib->grp->name);
|
||||
} else if (sysfs_attrib->attr.name) {
|
||||
debugf0("%s() file %s\n", __func__,
|
||||
debugf4("%s() file %s\n", __func__,
|
||||
sysfs_attrib->attr.name);
|
||||
sysfs_remove_file(kobj, &sysfs_attrib->attr);
|
||||
} else
|
||||
|
|
@ -979,7 +979,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
|
|||
debugf0("%s()\n", __func__);
|
||||
|
||||
/* remove all csrow kobjects */
|
||||
debugf0("%s() unregister this mci kobj\n", __func__);
|
||||
debugf4("%s() unregister this mci kobj\n", __func__);
|
||||
for (i = 0; i < mci->nr_csrows; i++) {
|
||||
if (mci->csrows[i].nr_pages > 0) {
|
||||
debugf0("%s() unreg csrow-%d\n", __func__, i);
|
||||
|
|
@ -989,18 +989,18 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
|
|||
|
||||
/* remove this mci instance's attribtes */
|
||||
if (mci->mc_driver_sysfs_attributes) {
|
||||
debugf0("%s() unregister mci private attributes\n", __func__);
|
||||
debugf4("%s() unregister mci private attributes\n", __func__);
|
||||
edac_remove_mci_instance_attributes(mci,
|
||||
mci->mc_driver_sysfs_attributes,
|
||||
&mci->edac_mci_kobj, 0);
|
||||
}
|
||||
|
||||
/* remove the symlink */
|
||||
debugf0("%s() remove_link\n", __func__);
|
||||
debugf4("%s() remove_link\n", __func__);
|
||||
sysfs_remove_link(&mci->edac_mci_kobj, EDAC_DEVICE_SYMLINK);
|
||||
|
||||
/* unregister this instance's kobject */
|
||||
debugf0("%s() remove_mci_instance\n", __func__);
|
||||
debugf4("%s() remove_mci_instance\n", __func__);
|
||||
kobject_put(&mci->edac_mci_kobj);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -594,6 +594,7 @@ static bool nb_noop_mce(u16 ec, u8 xec)
|
|||
|
||||
void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &boot_cpu_data;
|
||||
u16 ec = EC(m->status);
|
||||
u8 xec = XEC(m->status, 0x1f);
|
||||
u32 nbsh = (u32)(m->status >> 32);
|
||||
|
|
@ -602,9 +603,8 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
|
|||
pr_emerg(HW_ERR "Northbridge Error (node %d", node_id);
|
||||
|
||||
/* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */
|
||||
if ((boot_cpu_data.x86 == 0x10) &&
|
||||
(boot_cpu_data.x86_model > 7)) {
|
||||
if (nbsh & K8_NBSH_ERR_CPU_VAL)
|
||||
if (c->x86 == 0x10 && c->x86_model > 7) {
|
||||
if (nbsh & NBSH_ERR_CPU_VAL)
|
||||
core = nbsh & nb_err_cpumask;
|
||||
} else {
|
||||
u8 assoc_cpus = nbsh & nb_err_cpumask;
|
||||
|
|
@ -646,7 +646,7 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
|
|||
if (!fam_ops->nb_mce(ec, xec))
|
||||
goto wrong_nb_mce;
|
||||
|
||||
if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
|
||||
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
|
||||
if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
|
||||
nb_bus_decoder(node_id, m, nbcfg);
|
||||
|
||||
|
|
|
|||
|
|
@ -31,19 +31,10 @@
|
|||
#define R4(x) (((x) >> 4) & 0xf)
|
||||
#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
|
||||
|
||||
#define K8_NBSH 0x4C
|
||||
|
||||
#define K8_NBSH_VALID_BIT BIT(31)
|
||||
#define K8_NBSH_OVERFLOW BIT(30)
|
||||
#define K8_NBSH_UC_ERR BIT(29)
|
||||
#define K8_NBSH_ERR_EN BIT(28)
|
||||
#define K8_NBSH_MISCV BIT(27)
|
||||
#define K8_NBSH_VALID_ERROR_ADDR BIT(26)
|
||||
#define K8_NBSH_PCC BIT(25)
|
||||
#define K8_NBSH_ERR_CPU_VAL BIT(24)
|
||||
#define K8_NBSH_CECC BIT(14)
|
||||
#define K8_NBSH_UECC BIT(13)
|
||||
#define K8_NBSH_ERR_SCRUBER BIT(8)
|
||||
/*
|
||||
* F3x4C bits (MCi_STATUS' high half)
|
||||
*/
|
||||
#define NBSH_ERR_CPU_VAL BIT(24)
|
||||
|
||||
enum tt_ids {
|
||||
TT_INSTR = 0,
|
||||
|
|
@ -85,17 +76,6 @@ extern const char *pp_msgs[];
|
|||
extern const char *to_msgs[];
|
||||
extern const char *ii_msgs[];
|
||||
|
||||
/*
|
||||
* relevant NB regs
|
||||
*/
|
||||
struct err_regs {
|
||||
u32 nbcfg;
|
||||
u32 nbsh;
|
||||
u32 nbsl;
|
||||
u32 nbeah;
|
||||
u32 nbeal;
|
||||
};
|
||||
|
||||
/*
|
||||
* per-family decoder ops
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -517,7 +517,7 @@
|
|||
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
|
||||
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
|
||||
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
|
||||
#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
|
||||
#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
|
||||
#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604
|
||||
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
|
||||
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
|
||||
|
|
|
|||
Loading…
Reference in New Issue