bnx2x: FW assertion changes
This is mostly a semantic change which modifies the code parsing and printing of FW asserts. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ariel Elior
David S. Miller
parent
58fee00ffa
commit
97539f1e4f
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@ -650,119 +650,98 @@ static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
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bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
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}
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enum storms {
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XSTORM,
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TSTORM,
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CSTORM,
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USTORM,
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MAX_STORMS
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};
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#define STORMS_NUM 4
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#define REGS_IN_ENTRY 4
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static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
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enum storms storm,
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int entry)
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{
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switch (storm) {
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case XSTORM:
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return XSTORM_ASSERT_LIST_OFFSET(entry);
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case TSTORM:
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return TSTORM_ASSERT_LIST_OFFSET(entry);
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case CSTORM:
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return CSTORM_ASSERT_LIST_OFFSET(entry);
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case USTORM:
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return USTORM_ASSERT_LIST_OFFSET(entry);
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case MAX_STORMS:
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default:
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BNX2X_ERR("unknown storm\n");
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}
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return -EINVAL;
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}
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static int bnx2x_mc_assert(struct bnx2x *bp)
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{
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char last_idx;
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int i, rc = 0;
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u32 row0, row1, row2, row3;
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int i, j, rc = 0;
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enum storms storm;
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u32 regs[REGS_IN_ENTRY];
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u32 bar_storm_intmem[STORMS_NUM] = {
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BAR_XSTRORM_INTMEM,
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BAR_TSTRORM_INTMEM,
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BAR_CSTRORM_INTMEM,
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BAR_USTRORM_INTMEM
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};
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u32 storm_assert_list_index[STORMS_NUM] = {
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XSTORM_ASSERT_LIST_INDEX_OFFSET,
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TSTORM_ASSERT_LIST_INDEX_OFFSET,
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CSTORM_ASSERT_LIST_INDEX_OFFSET,
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USTORM_ASSERT_LIST_INDEX_OFFSET
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};
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char *storms_string[STORMS_NUM] = {
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"XSTORM",
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"TSTORM",
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"CSTORM",
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"USTORM"
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};
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/* XSTORM */
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last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
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XSTORM_ASSERT_LIST_INDEX_OFFSET);
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if (last_idx)
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BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
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for (storm = XSTORM; storm < MAX_STORMS; storm++) {
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last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
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storm_assert_list_index[storm]);
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if (last_idx)
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BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
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storms_string[storm], last_idx);
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/* print the asserts */
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for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
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/* print the asserts */
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for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
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/* read a single assert entry */
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for (j = 0; j < REGS_IN_ENTRY; j++)
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regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
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bnx2x_get_assert_list_entry(bp,
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storm,
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i) +
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sizeof(u32) * j);
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row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
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XSTORM_ASSERT_LIST_OFFSET(i));
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row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
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XSTORM_ASSERT_LIST_OFFSET(i) + 4);
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row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
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XSTORM_ASSERT_LIST_OFFSET(i) + 8);
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row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
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XSTORM_ASSERT_LIST_OFFSET(i) + 12);
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if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i, row3, row2, row1, row0);
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rc++;
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} else {
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break;
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/* log entry if it contains a valid assert */
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if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
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storms_string[storm], i, regs[3],
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regs[2], regs[1], regs[0]);
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rc++;
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} else {
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break;
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}
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}
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}
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/* TSTORM */
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last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
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TSTORM_ASSERT_LIST_INDEX_OFFSET);
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if (last_idx)
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BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
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/* print the asserts */
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for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
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row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
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TSTORM_ASSERT_LIST_OFFSET(i));
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row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
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TSTORM_ASSERT_LIST_OFFSET(i) + 4);
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row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
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TSTORM_ASSERT_LIST_OFFSET(i) + 8);
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row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
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TSTORM_ASSERT_LIST_OFFSET(i) + 12);
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if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i, row3, row2, row1, row0);
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rc++;
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} else {
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break;
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}
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}
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/* CSTORM */
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last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
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CSTORM_ASSERT_LIST_INDEX_OFFSET);
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if (last_idx)
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BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
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/* print the asserts */
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for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
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row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
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CSTORM_ASSERT_LIST_OFFSET(i));
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row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
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CSTORM_ASSERT_LIST_OFFSET(i) + 4);
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row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
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CSTORM_ASSERT_LIST_OFFSET(i) + 8);
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row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
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CSTORM_ASSERT_LIST_OFFSET(i) + 12);
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if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i, row3, row2, row1, row0);
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rc++;
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} else {
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break;
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}
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}
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/* USTORM */
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last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
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USTORM_ASSERT_LIST_INDEX_OFFSET);
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if (last_idx)
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BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
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/* print the asserts */
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for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
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row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
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USTORM_ASSERT_LIST_OFFSET(i));
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row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
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USTORM_ASSERT_LIST_OFFSET(i) + 4);
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row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
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USTORM_ASSERT_LIST_OFFSET(i) + 8);
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row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
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USTORM_ASSERT_LIST_OFFSET(i) + 12);
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if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i, row3, row2, row1, row0);
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rc++;
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} else {
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break;
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}
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}
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BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
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CHIP_IS_E1(bp) ? "everest1" :
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CHIP_IS_E1H(bp) ? "everest1h" :
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CHIP_IS_E2(bp) ? "everest2" : "everest3",
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BCM_5710_FW_MAJOR_VERSION,
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BCM_5710_FW_MINOR_VERSION,
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BCM_5710_FW_REVISION_VERSION);
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return rc;
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}
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