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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux 

net/mlx5: Add ability to read and write ECE options
  net/mlx5: Add support for RDMA TX FT headers modifying
  net/mlx5: Move iseg access helper routines close to mlx5_core driver
  net/mlx5: Cleanup mlx5_ifc_fte_match_set_misc2_bits
  net/mlx5: Add support in forward to namespace
  {IB/net}/mlx5: Simplify don't trap code
  net/mlx5: Replace zero-length array with flexible-array

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Saeed Mahameed 2020-05-29 14:38:02 -07:00
parent c223c7f22c 6b646a7e4a
commit 971ae1ed03
13 changed files with 168 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/infiniband/hw/mlx5/flow.c
View File

@ -404,7 +404,10 @@ static bool mlx5_ib_modify_header_supported(struct mlx5_ib_dev *dev)
{
return MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, max_modify_header_actions);
MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
max_modify_header_actions) ||
MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev,
max_modify_header_actions);
}
static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER)(

47
drivers/infiniband/hw/mlx5/main.c
View File

@ -3698,12 +3698,13 @@ static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
if (!dest_num)
rule_dst = NULL;
} else {
if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)
flow_act.action |=
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
if (is_egress)
flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
else
flow_act.action |=
dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
else if (dest_num)
flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
}
if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
@ -3747,30 +3748,6 @@ static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
}
static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
struct mlx5_ib_flow_prio *ft_prio,
struct ib_flow_attr *flow_attr,
struct mlx5_flow_destination *dst)
{
struct mlx5_ib_flow_handler *handler_dst = NULL;
struct mlx5_ib_flow_handler *handler = NULL;
handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
if (!IS_ERR(handler)) {
handler_dst = create_flow_rule(dev, ft_prio,
flow_attr, dst);
if (IS_ERR(handler_dst)) {
mlx5_del_flow_rules(handler->rule);
ft_prio->refcount--;
kfree(handler);
handler = handler_dst;
} else {
list_add(&handler_dst->list, &handler->list);
}
}
return handler;
}
enum {
LEFTOVERS_MC,
LEFTOVERS_UC,
@ -3974,15 +3951,11 @@ static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
}
if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
handler = create_dont_trap_rule(dev, ft_prio,
flow_attr, dst);
} else {
underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
mqp->underlay_qpn : 0;
handler = _create_flow_rule(dev, ft_prio, flow_attr,
dst, underlay_qpn, ucmd);
}
underlay_qpn = (mqp->flags & IB_QP_CREATE_SOURCE_QPN) ?
mqp->underlay_qpn :
0;
handler = _create_flow_rule(dev, ft_prio, flow_attr, dst,
underlay_qpn, ucmd);
} else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
handler = create_leftovers_rule(dev, ft_prio, flow_attr,

5
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
View File

@ -1936,6 +1936,11 @@ static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
cmd->alloc_dma);
}
static u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
int mlx5_cmd_init(struct mlx5_core_dev *dev)
{
int size = sizeof(struct mlx5_cmd_prot_block);

4
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
View File

@ -781,6 +781,10 @@ static int mlx5_cmd_modify_header_alloc(struct mlx5_flow_root_namespace *ns,
max_actions = MLX5_CAP_ESW_INGRESS_ACL(dev, max_modify_header_actions);
table_type = FS_FT_ESW_INGRESS_ACL;
break;
case MLX5_FLOW_NAMESPACE_RDMA_TX:
max_actions = MLX5_CAP_FLOWTABLE_RDMA_TX(dev, max_modify_header_actions);
table_type = FS_FT_RDMA_TX;
break;
default:
return -EOPNOTSUPP;
}

116
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
View File

@ -254,7 +254,7 @@ static void del_sw_flow_group(struct fs_node *node);
static void del_sw_fte(struct fs_node *node);
static void del_sw_prio(struct fs_node *node);
static void del_sw_ns(struct fs_node *node);
/* Delete rule (destination) is special case that
/* Delete rule (destination) is special case that
* requires to lock the FTE for all the deletion process.
*/
static void del_sw_hw_rule(struct fs_node *node);
@ -379,6 +379,12 @@ static struct fs_prio *find_prio(struct mlx5_flow_namespace *ns,
return NULL;
}
static bool is_fwd_next_action(u32 action)
{
return action & (MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO |
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS);
}
static bool check_valid_spec(const struct mlx5_flow_spec *spec)
{
int i;
@ -499,7 +505,7 @@ static void del_sw_hw_rule(struct fs_node *node)
fs_get_obj(rule, node);
fs_get_obj(fte, rule->node.parent);
trace_mlx5_fs_del_rule(rule);
if (rule->sw_action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (is_fwd_next_action(rule->sw_action)) {
mutex_lock(&rule->dest_attr.ft->lock);
list_del(&rule->next_ft);
mutex_unlock(&rule->dest_attr.ft->lock);
@ -823,6 +829,36 @@ static struct mlx5_flow_table *find_prev_chained_ft(struct fs_prio *prio)
return find_closest_ft(prio, true);
}
static struct fs_prio *find_fwd_ns_prio(struct mlx5_flow_root_namespace *root,
struct mlx5_flow_namespace *ns)
{
struct mlx5_flow_namespace *root_ns = &root->ns;
struct fs_prio *iter_prio;
struct fs_prio *prio;
fs_get_obj(prio, ns->node.parent);
list_for_each_entry(iter_prio, &root_ns->node.children, node.list) {
if (iter_prio == prio &&
!list_is_last(&prio->node.children, &iter_prio->node.list))
return list_next_entry(iter_prio, node.list);
}
return NULL;
}
static struct mlx5_flow_table *find_next_fwd_ft(struct mlx5_flow_table *ft,
struct mlx5_flow_act *flow_act)
{
struct mlx5_flow_root_namespace *root = find_root(&ft->node);
struct fs_prio *prio;
if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS)
prio = find_fwd_ns_prio(root, ft->ns);
else
fs_get_obj(prio, ft->node.parent);
return (prio) ? find_next_chained_ft(prio) : NULL;
}
static int connect_fts_in_prio(struct mlx5_core_dev *dev,
struct fs_prio *prio,
struct mlx5_flow_table *ft)
@ -973,6 +1009,10 @@ static int connect_fwd_rules(struct mlx5_core_dev *dev,
list_splice_init(&old_next_ft->fwd_rules, &new_next_ft->fwd_rules);
mutex_unlock(&old_next_ft->lock);
list_for_each_entry(iter, &new_next_ft->fwd_rules, next_ft) {
if ((iter->sw_action & MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS) &&
iter->ft->ns == new_next_ft->ns)
continue;
err = _mlx5_modify_rule_destination(iter, &dest);
if (err)
pr_err("mlx5_core: failed to modify rule to point on flow table %d\n",
@ -1074,6 +1114,7 @@ static struct mlx5_flow_table *__mlx5_create_flow_table(struct mlx5_flow_namespa
next_ft = unmanaged ? ft_attr->next_ft :
find_next_chained_ft(fs_prio);
ft->def_miss_action = ns->def_miss_action;
ft->ns = ns;
err = root->cmds->create_flow_table(root, ft, log_table_sz, next_ft);
if (err)
goto free_ft;
@ -1898,48 +1939,59 @@ mlx5_add_flow_rules(struct mlx5_flow_table *ft,
{
struct mlx5_flow_root_namespace *root = find_root(&ft->node);
static const struct mlx5_flow_spec zero_spec = {};
struct mlx5_flow_destination gen_dest = {};
struct mlx5_flow_destination *gen_dest = NULL;
struct mlx5_flow_table *next_ft = NULL;
struct mlx5_flow_handle *handle = NULL;
u32 sw_action = flow_act->action;
struct fs_prio *prio;
int i;
if (!spec)
spec = &zero_spec;
fs_get_obj(prio, ft->node.parent);
if (flow_act->action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (!fwd_next_prio_supported(ft))
return ERR_PTR(-EOPNOTSUPP);
if (num_dest)
return ERR_PTR(-EINVAL);
mutex_lock(&root->chain_lock);
next_ft = find_next_chained_ft(prio);
if (next_ft) {
gen_dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
gen_dest.ft = next_ft;
dest = &gen_dest;
num_dest = 1;
flow_act->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
} else {
mutex_unlock(&root->chain_lock);
return ERR_PTR(-EOPNOTSUPP);
}
if (!is_fwd_next_action(sw_action))
return _mlx5_add_flow_rules(ft, spec, flow_act, dest, num_dest);
if (!fwd_next_prio_supported(ft))
return ERR_PTR(-EOPNOTSUPP);
mutex_lock(&root->chain_lock);
next_ft = find_next_fwd_ft(ft, flow_act);
if (!next_ft) {
handle = ERR_PTR(-EOPNOTSUPP);
goto unlock;
}
gen_dest = kcalloc(num_dest + 1, sizeof(*dest),
GFP_KERNEL);
if (!gen_dest) {
handle = ERR_PTR(-ENOMEM);
goto unlock;
}
for (i = 0; i < num_dest; i++)
gen_dest[i] = dest[i];
gen_dest[i].type =
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
gen_dest[i].ft = next_ft;
dest = gen_dest;
num_dest++;
flow_act->action &= ~(MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO |
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS);
flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
handle = _mlx5_add_flow_rules(ft, spec, flow_act, dest, num_dest);
if (IS_ERR(handle))
goto unlock;
if (sw_action == MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO) {
if (!IS_ERR_OR_NULL(handle) &&
(list_empty(&handle->rule[0]->next_ft))) {
mutex_lock(&next_ft->lock);
list_add(&handle->rule[0]->next_ft,
&next_ft->fwd_rules);
mutex_unlock(&next_ft->lock);
handle->rule[0]->sw_action = MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
}
mutex_unlock(&root->chain_lock);
if (list_empty(&handle->rule[num_dest - 1]->next_ft)) {
mutex_lock(&next_ft->lock);
list_add(&handle->rule[num_dest - 1]->next_ft,
&next_ft->fwd_rules);
mutex_unlock(&next_ft->lock);
handle->rule[num_dest - 1]->sw_action = sw_action;
handle->rule[num_dest - 1]->ft = ft;
}
unlock:
mutex_unlock(&root->chain_lock);
kfree(gen_dest);
return handle;
}
EXPORT_SYMBOL(mlx5_add_flow_rules);

2
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
View File

@ -138,6 +138,7 @@ struct fs_node {
struct mlx5_flow_rule {
struct fs_node node;
struct mlx5_flow_table *ft;
struct mlx5_flow_destination dest_attr;
/* next_ft should be accessed under chain_lock and only of
* destination type is FWD_NEXT_fT.
@ -175,6 +176,7 @@ struct mlx5_flow_table {
u32 flags;
struct rhltable fgs_hash;
enum mlx5_flow_table_miss_action def_miss_action;
struct mlx5_flow_namespace *ns;
};
struct mlx5_ft_underlay_qp {

5
drivers/net/ethernet/mellanox/mlx5/core/main.c
View File

@ -177,6 +177,11 @@ static struct mlx5_profile profile[] = {
#define FW_PRE_INIT_TIMEOUT_MILI 120000
#define FW_INIT_WARN_MESSAGE_INTERVAL 20000
static int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
u32 warn_time_mili)
{

1
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
View File

@ -961,7 +961,6 @@ static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec)
spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1);
spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0);
spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a);
spec->metadata_reg_b = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_b);
}
static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec)

3
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View File

@ -554,8 +554,7 @@ struct mlx5dr_match_misc2 {
u32 metadata_reg_c_1; /* metadata_reg_c_1 */
u32 metadata_reg_c_0; /* metadata_reg_c_0 */
u32 metadata_reg_a; /* metadata_reg_a */
u32 metadata_reg_b; /* metadata_reg_b */
u8 reserved_auto2[8];
u8 reserved_auto2[12];
};
struct mlx5dr_match_misc3 {

12
include/linux/mlx5/driver.h
View File

@ -201,7 +201,7 @@ struct mlx5_rsc_debug {
void *object;
enum dbg_rsc_type type;
struct dentry *root;
struct mlx5_field_desc fields[0];
struct mlx5_field_desc fields[];
};
enum mlx5_dev_event {
@ -832,11 +832,6 @@ static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
}
static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
}
static inline u32 mlx5_base_mkey(const u32 key)
{
return key & 0xffffff00u;
@ -1028,11 +1023,6 @@ int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
u8 roce_version, u8 roce_l3_type, const u8 *gid,
const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
static inline int fw_initializing(struct mlx5_core_dev *dev)
{
return ioread32be(&dev->iseg->initializing) >> 31;
}
static inline u32 mlx5_mkey_to_idx(u32 mkey)
{
return mkey >> 8;

1
include/linux/mlx5/fs.h
View File

@ -42,6 +42,7 @@ enum {
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16,
MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17,
MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 18,
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS = 1 << 19,
};
enum {

96
include/linux/mlx5/mlx5_ifc.h
View File

@ -584,9 +584,7 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
u8 metadata_reg_a[0x20];
u8 metadata_reg_b[0x20];
u8 reserved_at_1c0[0x40];
u8 reserved_at_1a0[0x60];
};
struct mlx5_ifc_fte_match_set_misc3_bits {
@ -1210,7 +1208,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_99[0x2];
u8 log_max_qp[0x5];
u8 reserved_at_a0[0xb];
u8 reserved_at_a0[0x3];
u8 ece_support[0x1];
u8 reserved_at_a4[0x7];
u8 log_max_srq[0x5];
u8 reserved_at_b0[0x10];
@ -1703,7 +1703,7 @@ struct mlx5_ifc_wq_bits {
u8 reserved_at_140[0x4c0];
struct mlx5_ifc_cmd_pas_bits pas[0];
struct mlx5_ifc_cmd_pas_bits pas[];
};
struct mlx5_ifc_rq_num_bits {
@ -1921,7 +1921,7 @@ struct mlx5_ifc_resource_dump_menu_segment_bits {
u8 reserved_at_20[0x10];
u8 num_of_records[0x10];
struct mlx5_ifc_resource_dump_menu_record_bits record[0];
struct mlx5_ifc_resource_dump_menu_record_bits record[];
};
struct mlx5_ifc_resource_dump_resource_segment_bits {
@ -1933,7 +1933,7 @@ struct mlx5_ifc_resource_dump_resource_segment_bits {
u8 index2[0x20];
u8 payload[0][0x20];
u8 payload[][0x20];
};
struct mlx5_ifc_resource_dump_terminate_segment_bits {
@ -3010,7 +3010,7 @@ struct mlx5_ifc_flow_context_bits {
u8 reserved_at_1200[0x600];
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
};
enum {
@ -3303,7 +3303,7 @@ struct mlx5_ifc_rqtc_bits {
u8 reserved_at_e0[0x6a0];
struct mlx5_ifc_rq_num_bits rq_num[0];
struct mlx5_ifc_rq_num_bits rq_num[];
};
enum {
@ -3415,7 +3415,7 @@ struct mlx5_ifc_nic_vport_context_bits {
u8 reserved_at_7e0[0x20];
u8 current_uc_mac_address[0][0x40];
u8 current_uc_mac_address[][0x40];
};
enum {
@ -4218,7 +4218,8 @@ struct mlx5_ifc_rts2rts_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_rts2rts_qp_in_bits {
@ -4235,7 +4236,7 @@ struct mlx5_ifc_rts2rts_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -4248,7 +4249,8 @@ struct mlx5_ifc_rtr2rts_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_rtr2rts_qp_in_bits {
@ -4265,7 +4267,7 @@ struct mlx5_ifc_rtr2rts_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -4338,7 +4340,7 @@ struct mlx5_ifc_query_xrc_srq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_xrc_srq_in_bits {
@ -4616,7 +4618,7 @@ struct mlx5_ifc_query_srq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_srq_in_bits {
@ -4817,7 +4819,8 @@ struct mlx5_ifc_query_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
u8 opt_param_mask[0x20];
@ -4827,7 +4830,7 @@ struct mlx5_ifc_query_qp_out_bits {
u8 reserved_at_800[0x80];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_qp_in_bits {
@ -5160,7 +5163,7 @@ struct mlx5_ifc_query_hca_vport_pkey_out_bits {
u8 reserved_at_40[0x40];
struct mlx5_ifc_pkey_bits pkey[0];
struct mlx5_ifc_pkey_bits pkey[];
};
struct mlx5_ifc_query_hca_vport_pkey_in_bits {
@ -5196,7 +5199,7 @@ struct mlx5_ifc_query_hca_vport_gid_out_bits {
u8 gids_num[0x10];
u8 reserved_at_70[0x10];
struct mlx5_ifc_array128_auto_bits gid[0];
struct mlx5_ifc_array128_auto_bits gid[];
};
struct mlx5_ifc_query_hca_vport_gid_in_bits {
@ -5464,7 +5467,7 @@ struct mlx5_ifc_query_flow_counter_out_bits {
u8 reserved_at_40[0x40];
struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
struct mlx5_ifc_traffic_counter_bits flow_statistics[];
};
struct mlx5_ifc_query_flow_counter_in_bits {
@ -5558,7 +5561,7 @@ struct mlx5_ifc_query_eq_out_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_eq_in_bits {
@ -5583,7 +5586,7 @@ struct mlx5_ifc_packet_reformat_context_in_bits {
u8 reserved_at_20[0x10];
u8 reformat_data[2][0x8];
u8 more_reformat_data[0][0x8];
u8 more_reformat_data[][0x8];
};
struct mlx5_ifc_query_packet_reformat_context_out_bits {
@ -5594,7 +5597,7 @@ struct mlx5_ifc_query_packet_reformat_context_out_bits {
u8 reserved_at_40[0xa0];
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
};
struct mlx5_ifc_query_packet_reformat_context_in_bits {
@ -5833,7 +5836,7 @@ struct mlx5_ifc_query_cq_out_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_query_cq_in_bits {
@ -6440,7 +6443,7 @@ struct mlx5_ifc_modify_cq_in_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_modify_cong_status_out_bits {
@ -6504,7 +6507,7 @@ struct mlx5_ifc_manage_pages_out_bits {
u8 reserved_at_60[0x20];
u8 pas[0][0x40];
u8 pas[][0x40];
};
enum {
@ -6526,7 +6529,7 @@ struct mlx5_ifc_manage_pages_in_bits {
u8 input_num_entries[0x20];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_mad_ifc_out_bits {
@ -6582,7 +6585,8 @@ struct mlx5_ifc_init2rtr_qp_out_bits {
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
u8 reserved_at_40[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_init2rtr_qp_in_bits {
@ -6599,7 +6603,7 @@ struct mlx5_ifc_init2rtr_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -7481,7 +7485,7 @@ struct mlx5_ifc_create_xrc_srq_in_bits {
u8 reserved_at_300[0x580];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_tis_out_bits {
@ -7557,7 +7561,7 @@ struct mlx5_ifc_create_srq_in_bits {
u8 reserved_at_280[0x600];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_sq_out_bits {
@ -7695,7 +7699,7 @@ struct mlx5_ifc_create_qp_out_bits {
u8 reserved_at_40[0x8];
u8 qpn[0x18];
u8 reserved_at_60[0x20];
u8 ece[0x20];
};
struct mlx5_ifc_create_qp_in_bits {
@ -7709,7 +7713,7 @@ struct mlx5_ifc_create_qp_in_bits {
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
u8 ece[0x20];
struct mlx5_ifc_qpc_bits qpc;
@ -7718,7 +7722,7 @@ struct mlx5_ifc_create_qp_in_bits {
u8 wq_umem_valid[0x1];
u8 reserved_at_861[0x1f];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_psv_out_bits {
@ -7789,7 +7793,7 @@ struct mlx5_ifc_create_mkey_in_bits {
u8 reserved_at_320[0x560];
u8 klm_pas_mtt[0][0x20];
u8 klm_pas_mtt[][0x20];
};
enum {
@ -7922,7 +7926,7 @@ struct mlx5_ifc_create_eq_in_bits {
u8 reserved_at_3c0[0x4c0];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_create_dct_out_bits {
@ -7979,7 +7983,7 @@ struct mlx5_ifc_create_cq_in_bits {
u8 cq_umem_valid[0x1];
u8 reserved_at_2e1[0x59f];
u8 pas[0][0x40];
u8 pas[][0x40];
};
struct mlx5_ifc_config_int_moderation_out_bits {
@ -8335,7 +8339,7 @@ struct mlx5_ifc_access_register_out_bits {
u8 reserved_at_40[0x40];
u8 register_data[0][0x20];
u8 register_data[][0x20];
};
enum {
@ -8355,7 +8359,7 @@ struct mlx5_ifc_access_register_in_bits {
u8 argument[0x20];
u8 register_data[0][0x20];
u8 register_data[][0x20];
};
struct mlx5_ifc_sltp_reg_bits {
@ -9372,7 +9376,7 @@ struct mlx5_ifc_cmd_in_bits {
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 command[0][0x20];
u8 command[][0x20];
};
struct mlx5_ifc_cmd_if_box_bits {
@ -9666,7 +9670,7 @@ struct mlx5_ifc_mcqi_reg_bits {
u8 reserved_at_a0[0x10];
u8 data_size[0x10];
union mlx5_ifc_mcqi_reg_data_bits data[0];
union mlx5_ifc_mcqi_reg_data_bits data[];
};
struct mlx5_ifc_mcc_reg_bits {
@ -10252,7 +10256,7 @@ struct mlx5_ifc_umem_bits {
u8 num_of_mtt[0x40];
struct mlx5_ifc_mtt_bits mtt[0];
struct mlx5_ifc_mtt_bits mtt[];
};
struct mlx5_ifc_uctx_bits {
@ -10377,7 +10381,7 @@ struct mlx5_ifc_mtrc_stdb_bits {
u8 reserved_at_4[0x4];
u8 read_size[0x18];
u8 start_offset[0x20];
u8 string_db_data[0];
u8 string_db_data[];
};
struct mlx5_ifc_mtrc_ctrl_bits {
@ -10431,7 +10435,7 @@ struct mlx5_ifc_query_esw_functions_out_bits {
struct mlx5_ifc_host_params_context_bits host_params_context;
u8 reserved_at_280[0x180];
u8 host_sf_enable[0][0x40];
u8 host_sf_enable[][0x40];
};
struct mlx5_ifc_sf_partition_bits {
@ -10451,7 +10455,7 @@ struct mlx5_ifc_query_sf_partitions_out_bits {
u8 reserved_at_60[0x20];
struct mlx5_ifc_sf_partition_bits sf_partition[0];
struct mlx5_ifc_sf_partition_bits sf_partition[];
};
struct mlx5_ifc_query_sf_partitions_in_bits {

2
include/linux/mlx5/qp.h
View File

@ -408,7 +408,7 @@ struct mlx5_wqe_signature_seg {
struct mlx5_wqe_inline_seg {
__be32 byte_count;
__be32 data[0];
__be32 data[];
};
enum mlx5_sig_type {