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ata: pata_at91.c bugfix for high master clock 

The AT91SAM9 microcontrollers with master clock higher then 105 MHz
and PIO0, have overflow of the NCS_RD_PULSE value in the MSB. This
lead to "NCS_RD_PULSE" pulse longer then "NRD_CYCLE" pulse and driver
does not detect ATA device.

Signed-off-by: Igor Plyatov <plyatov@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Igor Plyatov 2011-03-28 16:56:15 +04:00 committed by Jeff Garzik
parent 181e3ceaba
commit 9719b8f5bc
1 changed files with 7 additions and 1 deletions
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8
drivers/ata/pata_at91.c
View File

@ -33,11 +33,12 @@
#define DRV_NAME "pata_at91"
#define DRV_VERSION "0.1"
#define DRV_VERSION "0.2"
#define CF_IDE_OFFSET 0x00c00000
#define CF_ALT_IDE_OFFSET 0x00e00000
#define CF_IDE_RES_SIZE 0x08
#define NCS_RD_PULSE_LIMIT 0x3f /* maximal value for pulse bitfields */
struct at91_ide_info {
unsigned long mode;
@ -109,6 +110,11 @@ static void set_smc_timing(struct device *dev,
/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
ncs_read_setup = 1;
ncs_read_pulse = read_cycle - 2;
if (ncs_read_pulse > NCS_RD_PULSE_LIMIT) {
ncs_read_pulse = NCS_RD_PULSE_LIMIT;
dev_warn(dev, "ncs_read_pulse limited to maximal value %lu\n",
ncs_read_pulse);
}
/* Write timings same as read timings */
write_cycle = read_cycle;