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Renesas ARM DT updates for v5.11 

- Touch screen and OV5640 camera support for the iWave RainboW Qseven
     board (G21D), and its camera expansion board,
   - Support for the AISTARVISION MIPI Adapter V2.1 board connected to
     HiHope RZ/G2 boards,
   - SPI (MSIOF) support for the R-Car M3-W+ SoC,
   - Digital Radio Interface (DRIF) support for the R-Car M3-N SoC,
   - Initial support for the R-Car M3-W+ ULCB/Kingfisher board combo,
   - Minor fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.11

  - Touch screen and OV5640 camera support for the iWave RainboW Qseven
    board (G21D), and its camera expansion board,
  - Support for the AISTARVISION MIPI Adapter V2.1 board connected to
    HiHope RZ/G2 boards,
  - SPI (MSIOF) support for the R-Car M3-W+ SoC,
  - Digital Radio Interface (DRIF) support for the R-Car M3-N SoC,
  - Initial support for the R-Car M3-W+ ULCB/Kingfisher board combo,
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: hihope-rev4: Add a comment explaining switch SW2404
  arm64: dts: renesas: r8a77961: ulcb-kf: Initial device tree
  arm64: dts: renesas: r8a77961: Add CAN{0,1} placeholder nodes
  arm64: dts: renesas: beacon-renesom-baseboard: Move connector node out of hd3ss3220 device
  arm64: dts: renesas: cat874: Move connector node out of hd3ss3220 device
  arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling
  arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling
  arm64: dts: renesas: r8a77965: Add DRIF support
  arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2N
  arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2M
  arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H
  arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro for each sensor
  arm64: dts: renesas: cat875: Remove rxc-skew-ps from ethernet-phy node
  arm64: dts: renesas: hihope-rzg2-ex: Drop rxc-skew-ps from ethernet-phy node
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances
  arm64: dts: renesas: r8a77961: Add MSIOF nodes
  arm64: dts: renesas: Align GPIO hog names with dtschema
  ARM: dts: r8a7742-iwg21d-q7: Add LCD support

Link: https://lore.kernel.org/r/20201113150854.3923885-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-11-23 16:48:48 +01:00
parent f8394f232b 43bba65761
commit 95f595d1f0
35 changed files with 851 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

222
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
View File

@ -20,6 +20,30 @@
serial5 = &hscif0;
ethernet1 = &ether;
};
mclk_cam1: mclk-cam1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
mclk_cam2: mclk-cam2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
mclk_cam3: mclk-cam3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
mclk_cam4: mclk-cam4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
&avb {
@ -47,6 +71,19 @@
};
};
&gpio0 {
/* Disable hogging GP0_18 to output LOW */
/delete-node/ qspi_en;
/* Hog GP0_18 to output HIGH to enable VIN2 */
vin2_en {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "VIN2_EN";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
@ -54,6 +91,94 @@
status = "okay";
};
&i2c0 {
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam1>;
clock-names = "xclk";
port {
ov5640_0: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin0ep>;
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam2>;
clock-names = "xclk";
port {
ov5640_1: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin1ep>;
};
};
};
};
&i2c2 {
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam3>;
clock-names = "xclk";
port {
ov5640_2: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin2ep>;
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&mclk_cam4>;
clock-names = "xclk";
port {
ov5640_3: endpoint {
bus-width = <8>;
data-shift = <2>;
bus-type = <6>;
pclk-sample = <1>;
remote-endpoint = <&vin3ep>;
};
};
};
};
&pfc {
can0_pins: can0 {
groups = "can0_data_d";
@ -70,6 +195,16 @@
function = "hscif0";
};
i2c1_pins: i2c1 {
groups = "i2c1_c";
function = "i2c1";
};
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@ -84,6 +219,31 @@
groups = "scifb1_data";
function = "scifb1";
};
vin0_8bit_pins: vin0 {
groups = "vin0_data8", "vin0_clk", "vin0_sync";
function = "vin0";
};
vin1_8bit_pins: vin1 {
groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b";
function = "vin1";
};
vin2_pins: vin2 {
groups = "vin2_g8", "vin2_clk";
function = "vin2";
};
vin3_pins: vin3 {
groups = "vin3_data8", "vin3_clk", "vin3_sync";
function = "vin3";
};
};
&qspi {
/* Pins shared with VIN2, keep status disabled */
status = "disabled";
};
&scif0 {
@ -106,3 +266,65 @@
rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
};
&vin0 {
/*
* Set SW2 switch on the SOM to 'ON'
* Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
*/
status = "okay";
pinctrl-0 = <&vin0_8bit_pins>;
pinctrl-names = "default";
port {
vin0ep: endpoint {
remote-endpoint = <&ov5640_0>;
bus-width = <8>;
bus-type = <6>;
};
};
};
&vin1 {
/* Set SW1 switch on the SOM to 'ON' */
status = "okay";
pinctrl-0 = <&vin1_8bit_pins>;
pinctrl-names = "default";
port {
vin1ep: endpoint {
remote-endpoint = <&ov5640_1>;
bus-width = <8>;
bus-type = <6>;
};
};
};
&vin2 {
status = "okay";
pinctrl-0 = <&vin2_pins>;
pinctrl-names = "default";
port {
vin2ep: endpoint {
remote-endpoint = <&ov5640_2>;
bus-width = <8>;
data-shift = <8>;
bus-type = <6>;
};
};
};
&vin3 {
status = "okay";
pinctrl-0 = <&vin3_pins>;
pinctrl-names = "default";
port {
vin3ep: endpoint {
remote-endpoint = <&ov5640_3>;
bus-width = <8>;
bus-type = <6>;
};
};
};

99
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
View File

@ -30,6 +30,7 @@
/dts-v1/;
#include "r8a7742-iwg21m.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
@ -52,6 +53,16 @@
clock-frequency = <26000000>;
};
lcd_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&tpu 2 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
pinctrl-0 = <&backlight_pins>;
pinctrl-names = "default";
default-brightness-level = <7>;
enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
@ -62,6 +73,41 @@
};
};
lvds-receiver {
compatible = "ti,ds90cf384a", "lvds-decoder";
power-supply = <&vcc_3v3_tft1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_receiver_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
lvds_receiver_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
panel {
compatible = "edt,etm0700g0dh6";
backlight = <&lcd_backlight>;
power-supply = <&vcc_3v3_tft1>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds_receiver_out>;
};
};
};
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
@ -85,6 +131,17 @@
};
};
vcc_3v3_tft1: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3-tft1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
startup-delay-us = <500>;
gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
compatible = "regulator-fixed";
@ -139,6 +196,16 @@
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p5v>;
};
touch: touchpanel@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
interrupt-parent = <&gpio0>;
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
/* GP1_29 is also shared with audio codec reset pin */
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
vcc-supply = <&vcc_3v3_tft1>;
};
};
&can1 {
@ -152,6 +219,18 @@
status = "okay";
};
&du {
status = "okay";
};
&gpio0 {
touch-interrupt {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
input;
};
};
&gpio1 {
can-trx-en-gpio{
gpio-hog;
@ -167,6 +246,17 @@
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&lvds_receiver_in>;
};
};
};
};
&msiof0 {
pinctrl-0 = <&msiof0_pins>;
pinctrl-names = "default";
@ -229,6 +319,11 @@
function = "avb";
};
backlight_pins: backlight {
groups = "tpu0_to2";
function = "tpu0";
};
can1_pins: can1 {
groups = "can1_data_b";
function = "can1";
@ -335,6 +430,10 @@
shared-pin;
};
&tpu {
status = "okay";
};
&usbphy {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/Makefile
View File

@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
@ -10,6 +11,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
@ -22,6 +24,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb
@ -39,6 +42,7 @@ dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb

4
arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
View File

@ -61,7 +61,7 @@
};
};
&MIPI_PARENT_I2C {
&MIPI_OV5645_PARENT_I2C {
ov5645: ov5645@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
@ -77,7 +77,9 @@
};
};
};
};
&MIPI_IMX219_PARENT_I2C {
imx219: imx219@10 {
compatible = "sony,imx219";
reg = <0x10>;

67
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -223,6 +223,29 @@
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
};
&audio_clk_a {
@ -427,20 +450,19 @@
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
hd3ss3220_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
@ -714,9 +736,20 @@
status = "okay";
usb-role-switch;
port {
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_ep>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};

3
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -55,7 +55,8 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {

1
arch/arm64/boot/dts/renesas/cat875.dtsi
View File

@ -21,7 +21,6 @@
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;

6
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View File

@ -91,7 +91,11 @@
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
/* update <audio_clk_b> to <cs2000> */
/*
* Update <audio_clk_b> to <cs2000>
* Switch SW2404 should be at position 1 so that clock from
* CS2000 is connected to AUDIO_CLKB_A
*/
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

109
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi Normal file
View File

@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#define MIPI_OV5645_PARENT_I2C i2c2
#define MIPI_IMX219_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
&csi20 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&ov5645_ep>;
};
};
};
};
&csi40 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&imx219_ep>;
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
};
&imx219 {
port {
imx219_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
remote-endpoint = <&csi40_in>;
};
};
};
&ov5645 {
enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
port {
ov5645_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi20_in>;
};
};
};
&pfc {
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};

3
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View File

@ -19,11 +19,10 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

29
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1-hihope-rzg2m-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
};
/*
* On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode.
* HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and
* imx219 as the imx219 endpoint driver supports only 2 lane mode.
*/
&csi40 {
status = "disabled";
};
&imx219 {
status = "disabled";
};

2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -1115,6 +1115,8 @@
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

16
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1-hihope-rzg2n-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
};

2
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -989,6 +989,8 @@
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

67
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
View File

@ -129,6 +129,29 @@
#clock-cells = <0>;
clock-frequency = <74250000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
};
&audio_clk_a {
@ -186,20 +209,19 @@
interrupt-parent = <&gpio6>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
hd3ss3220_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
@ -405,9 +427,20 @@
status = "okay";
usb-role-switch;
port {
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_ep>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};

3
arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
View File

@ -8,7 +8,8 @@
/dts-v1/;
#include "r8a774c0-ek874.dts"
#define MIPI_PARENT_I2C i2c3
#define MIPI_OV5645_PARENT_I2C i2c3
#define MIPI_IMX219_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
/ {

1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -960,6 +960,7 @@
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

16
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1-hihope-rzg2h-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
};

2
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -1212,6 +1212,8 @@
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts
View File

@ -118,7 +118,7 @@
};
&pca9654 {
pcie_sata_switch {
pcie-sata-switch-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */

2
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -1250,6 +1250,8 @@
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -1126,6 +1126,8 @@
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

15
arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB Kingfisher board
*
* Copyright (C) 2020 Eugeniu Rosca <rosca.eugeniu@gmail.com>
*/
#include "r8a77961-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3ULCB Kingfisher board based on r8a77961";
compatible = "shimafuji,kingfisher", "renesas,m3ulcb",
"renesas,r8a77961";
};

74
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -1012,11 +1012,23 @@
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@e6c30000 {
reg = <0 0xe6c30000 0 0x1000>;
/* placeholder */
};
can1: can@e6c38000 {
reg = <0 0xe6c38000 0 0x1000>;
/* placeholder */
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
@ -1187,6 +1199,68 @@
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a77961",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a77961",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a77961",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a77961",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vin0: video@e6ef0000 {
reg = <0 0xe6ef0000 0 0x1000>;
/* placeholder */

2
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
View File

@ -55,7 +55,7 @@
};
&pca9654 {
pcie_sata_switch {
pcie-sata-switch-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */

122
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -988,6 +988,8 @@
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -1550,6 +1552,126 @@
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x84>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x84>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x84>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x84>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x84>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x84>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x84>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x84>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required

3
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@ -81,7 +81,8 @@
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {

3
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@ -102,7 +102,8 @@
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {

2
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -615,6 +615,8 @@
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -667,6 +667,8 @@
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <2000>;
iommus = <&ipmmu_ds1 33>;
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -938,6 +938,7 @@
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -628,6 +628,7 @@
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <1800>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -324,7 +324,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {

14
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@ -143,49 +143,49 @@
interrupt-parent = <&gpio6>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
audio_out_off {
audio-out-off-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */
output-high;
line-name = "Audio_Out_OFF";
};
hub_pwen {
hub-pwen-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "HUB pwen";
};
hub_rst {
hub-rst-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "HUB rst";
};
otg_extlpn {
otg-extlpn-hog {
gpio-hog;
gpios = <9 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "OTG EXTLPn";
};
otg_offvbusn {
otg-offvbusn-hog {
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "OTG OFFVBUSn";
};
sd-wifi-mux {
sd-wifi-mux-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-low; /* Connect WL1837 */
line-name = "SD WiFi mux";
};
snd_rst {
snd-rst-hog {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */
output-high;

2
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -144,7 +144,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {