b43: Add more N-PHY init code
This also adds lots of TODOs. Oh well. Lots of work. :) Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Michael Buesch
David S. Miller
parent
c09c7237ea
commit
95b66bad55
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@ -29,6 +29,8 @@
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#include "nphy.h"
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#include "tables_nphy.h"
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#include <linux/delay.h>
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void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
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{//TODO
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@ -191,9 +193,297 @@ void b43_nphy_radio_turn_off(struct b43_wldev *dev)
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~B43_NPHY_RFCTL_CMD_EN);
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}
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#define ntab_upload(dev, offset, data) do { \
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unsigned int i; \
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for (i = 0; i < (offset##_SIZE); i++) \
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b43_ntab_write(dev, (offset) + i, (data)[i]); \
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} while (0)
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/* Upload the N-PHY tables. */
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static void b43_nphy_tables_init(struct b43_wldev *dev)
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{
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/* Static tables */
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ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
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ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
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ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
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ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
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ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
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ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
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ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
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ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
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ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
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ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
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ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
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ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
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ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
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ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
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/* Volatile tables */
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ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
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ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
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ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
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ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
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ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
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ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
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ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
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ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
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ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
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ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
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ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
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ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
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}
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static void b43_nphy_workarounds(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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unsigned int i;
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b43_phy_set(dev, B43_NPHY_IQFLIP,
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B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
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//FIXME the following condition is different in the specs.
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if (1 /* FIXME band is 2.4GHz */) {
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b43_phy_set(dev, B43_NPHY_CLASSCTL,
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B43_NPHY_CLASSCTL_CCKEN);
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} else {
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b43_phy_mask(dev, B43_NPHY_CLASSCTL,
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~B43_NPHY_CLASSCTL_CCKEN);
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}
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b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
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b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
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/* Fixup some tables */
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
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b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
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//TODO set RF sequence
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/* Set narrowband clip threshold */
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b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
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b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
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/* Set wideband clip 2 threshold */
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b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
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~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
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~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
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/* Set Clip 2 detect */
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b43_phy_set(dev, B43_NPHY_C1_CGAINI,
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B43_NPHY_C1_CGAINI_CL2DETECT);
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b43_phy_set(dev, B43_NPHY_C2_CGAINI,
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B43_NPHY_C2_CGAINI_CL2DETECT);
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if (0 /*FIXME*/) {
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/* Set dwell lengths */
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b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
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b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
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/* Set gain backoff */
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b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
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~B43_NPHY_C1_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
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~B43_NPHY_C2_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
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/* Set HPVGA2 index */
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b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
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~B43_NPHY_C1_INITGAIN_HPVGA2,
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6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
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~B43_NPHY_C2_INITGAIN_HPVGA2,
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6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
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//FIXME verify that the specs really mean to use autoinc here.
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for (i = 0; i < 3; i++)
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b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
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}
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/* Set minimum gain value */
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b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
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~B43_NPHY_C1_MINGAIN,
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23 << B43_NPHY_C1_MINGAIN_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
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~B43_NPHY_C2_MINGAIN,
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23 << B43_NPHY_C2_MINGAIN_SHIFT);
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if (phy->rev < 2) {
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b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
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~B43_NPHY_SCRAM_SIGCTL_SCM);
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}
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/* Set phase track alpha and beta */
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b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
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b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
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b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
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b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
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b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
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}
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static void b43_nphy_reset_cca(struct b43_wldev *dev)
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{
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u16 bbcfg;
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
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bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
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b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG,
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bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
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}
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enum b43_nphy_rf_sequence {
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B43_RFSEQ_RX2TX,
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B43_RFSEQ_TX2RX,
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B43_RFSEQ_RESET2RX,
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B43_RFSEQ_UPDATE_GAINH,
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B43_RFSEQ_UPDATE_GAINL,
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B43_RFSEQ_UPDATE_GAINU,
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};
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static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
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enum b43_nphy_rf_sequence seq)
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{
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static const u16 trigger[] = {
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[B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
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[B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
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[B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
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[B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
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[B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
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[B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
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};
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int i;
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B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
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b43_phy_set(dev, B43_NPHY_RFSEQMODE,
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B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
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b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
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for (i = 0; i < 200; i++) {
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if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
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goto ok;
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msleep(1);
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}
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b43err(dev->wl, "RF sequence status timeout\n");
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ok:
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b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
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~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
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}
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static void b43_nphy_bphy_init(struct b43_wldev *dev)
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{
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unsigned int i;
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u16 val;
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val = 0x1E1F;
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for (i = 0; i < 14; i++) {
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b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
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val -= 0x202;
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}
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val = 0x3E3F;
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for (i = 0; i < 16; i++) {
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b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
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val -= 0x202;
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}
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b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
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}
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/* RSSI Calibration */
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static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
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{
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//TODO
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}
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int b43_phy_initn(struct b43_wldev *dev)
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{
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b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
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struct b43_phy *phy = &dev->phy;
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u16 tmp;
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//TODO: Spectral management
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b43_nphy_tables_init(dev);
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/* Clear all overrides */
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b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
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b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
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~(B43_NPHY_RFSEQMODE_CAOVER |
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B43_NPHY_RFSEQMODE_TROVER));
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b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
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tmp = (phy->rev < 2) ? 64 : 59;
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b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
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~B43_NPHY_BPHY_CTL3_SCALE,
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tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
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b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
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b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
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b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
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b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
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//TODO MIMO-Config
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//TODO Update TX/RX chain
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if (phy->rev < 2) {
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b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
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b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
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}
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b43_nphy_workarounds(dev);
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b43_nphy_reset_cca(dev);
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
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//TODO read core1/2 clip1 thres regs
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if (1 /* FIXME Band is 2.4GHz */)
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b43_nphy_bphy_init(dev);
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//TODO disable TX power control
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//TODO Fix the TX power settings
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//TODO Init periodic calibration with reason 3
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b43_nphy_rssi_cal(dev, 2);
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b43_nphy_rssi_cal(dev, 0);
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b43_nphy_rssi_cal(dev, 1);
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//TODO get TX gain
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//TODO init superswitch
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//TODO calibrate LO
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//TODO idle TSSI TX pctl
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//TODO TX power control power setup
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//TODO table writes
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//TODO TX power control coefficients
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//TODO enable TX power control
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//TODO control antenna selection
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//TODO init radar detection
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//TODO reset channel if changed
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b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
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return 0;
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}
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@ -25,8 +25,11 @@
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#define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
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#define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */
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#define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
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#define B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0
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#define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
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#define B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5
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#define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */
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#define B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10
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#define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
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#define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */
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#define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
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@ -69,29 +72,32 @@
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#define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */
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#define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */
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#define B43_NPHY_C2_DESPWR B43_PHY_N(0x018 + 22) /* Core 2 desired power */
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#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x019 + 22) /* Core 2 CCK desired power */
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#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x01A + 22) /* Core 2 barely clip backoff */
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#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x01B + 22) /* Core 2 CCK barely clip backoff */
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#define B43_NPHY_C2_CGAINI B43_PHY_N(0x01C + 22) /* Core 2 compute gain info */
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#define B43_NPHY_C2_DESPWR B43_PHY_N(0x02E) /* Core 2 desired power */
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#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x02F) /* Core 2 CCK desired power */
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#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x030) /* Core 2 barely clip backoff */
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#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */
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#define B43_NPHY_C2_CGAINI B43_PHY_N(0x032) /* Core 2 compute gain info */
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#define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
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#define B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0
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#define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
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#define B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5
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#define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */
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#define B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10
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#define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
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#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x01D + 22) /* Core 2 CCK compute gain info */
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#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x033) /* Core 2 CCK compute gain info */
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#define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
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#define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
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#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x01E + 22) /* Core 2 min/max gain */
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||||
#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x034) /* Core 2 min/max gain */
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#define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */
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||||
#define B43_NPHY_C2_MINGAIN_SHIFT 0
|
||||
#define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */
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||||
#define B43_NPHY_C2_MAXGAIN_SHIFT 8
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||||
#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x01F + 22) /* Core 2 CCK min/max gain */
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||||
#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x035) /* Core 2 CCK min/max gain */
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||||
#define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */
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||||
#define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0
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||||
#define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */
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||||
#define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8
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||||
#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x020 + 22) /* Core 2 initial gain code */
|
||||
#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x036) /* Core 2 initial gain code */
|
||||
#define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */
|
||||
#define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */
|
||||
#define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1
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||||
|
|
@ -101,23 +107,23 @@
|
|||
#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
|
||||
#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
|
||||
#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
|
||||
#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x021 + 22) /* Core 2 clip1 high gain code */
|
||||
#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x022 + 22) /* Core 2 clip1 medium gain code */
|
||||
#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x023 + 22) /* Core 2 clip1 low gain code */
|
||||
#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x024 + 22) /* Core 2 clip2 gain code */
|
||||
#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x025 + 22) /* Core 2 filter gain */
|
||||
#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x026 + 22) /* Core 2 LPF Q HP F bandwidth */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x027 + 22) /* Core 2 clip wideband threshold */
|
||||
#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
|
||||
#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
|
||||
#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
|
||||
#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
|
||||
#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
|
||||
#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0
|
||||
#define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
|
||||
#define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6
|
||||
#define B43_NPHY_C2_W1THRES B43_PHY_N(0x028 + 22) /* Core 2 W1 threshold */
|
||||
#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x029 + 22) /* Core 2 ED threshold */
|
||||
#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x02A + 22) /* Core 2 small sig threshold */
|
||||
#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x02B + 22) /* Core 2 NB clip threshold */
|
||||
#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x02C + 22) /* Core 2 clip1 threshold */
|
||||
#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x02D + 22) /* Core 2 clip2 threshold */
|
||||
#define B43_NPHY_C2_W1THRES B43_PHY_N(0x03E) /* Core 2 W1 threshold */
|
||||
#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x03F) /* Core 2 ED threshold */
|
||||
#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x040) /* Core 2 small sig threshold */
|
||||
#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x041) /* Core 2 NB clip threshold */
|
||||
#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x042) /* Core 2 clip1 threshold */
|
||||
#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x043) /* Core 2 clip2 threshold */
|
||||
|
||||
#define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */
|
||||
#define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */
|
||||
|
|
@ -225,7 +231,7 @@
|
|||
#define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */
|
||||
#define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */
|
||||
#define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */
|
||||
#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scran signal control */
|
||||
#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */
|
||||
#define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */
|
||||
#define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0
|
||||
#define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
|
||||
|
|
|
|||
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Reference in New Issue