ARM: 8055/1: cacheflush: use -st dsb option for ensuring completion
dsb st can be used to ensure completion of pending cache maintenance operations, so use it for the v7 cache maintenance operations. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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static inline void __flush_icache_all(void)
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static inline void __flush_icache_all(void)
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{
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{
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__flush_icache_preferred();
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__flush_icache_preferred();
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dsb();
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dsb(ishst);
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}
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}
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/*
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/*
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@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
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bgt 2b
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bgt 2b
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cmp r2, #0
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cmp r2, #0
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bgt 1b
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bgt 1b
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dsb
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dsb st
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isb
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isb
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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ENDPROC(v7_invalidate_l1)
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@ -166,7 +166,7 @@ skip:
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finished:
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finished:
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mov r10, #0 @ swith back to cache level 0
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb
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dsb st
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isb
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isb
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_flush_dcache_all)
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ENDPROC(v7_flush_dcache_all)
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@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
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add r0, r0, r2
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add r0, r0, r2
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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dsb
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dsb st
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_flush_kern_dcache_area)
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ENDPROC(v7_flush_kern_dcache_area)
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@ -368,7 +368,7 @@ v7_dma_inv_range:
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add r0, r0, r2
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add r0, r0, r2
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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dsb
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dsb st
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_dma_inv_range)
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ENDPROC(v7_dma_inv_range)
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@ -390,7 +390,7 @@ v7_dma_clean_range:
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add r0, r0, r2
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add r0, r0, r2
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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dsb
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dsb st
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_dma_clean_range)
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ENDPROC(v7_dma_clean_range)
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@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
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add r0, r0, r2
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add r0, r0, r2
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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dsb
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dsb st
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mov pc, lr
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mov pc, lr
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ENDPROC(v7_dma_flush_range)
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ENDPROC(v7_dma_flush_range)
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@ -1465,7 +1465,7 @@ void __init early_paging_init(const struct machine_desc *mdesc,
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* just complicate the code.
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* just complicate the code.
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*/
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*/
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flush_cache_louis();
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flush_cache_louis();
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dsb();
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dsb(ishst);
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isb();
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isb();
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/* remap level 1 table */
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/* remap level 1 table */
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