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ARM: 8055/1: cacheflush: use -st dsb option for ensuring completion 

dsb st can be used to ensure completion of pending cache maintenance
operations, so use it for the v7 cache maintenance operations.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Will Deacon 2014-05-09 18:36:27 +01:00 committed by Russell King
parent cd000cf650
commit 9581960a40
3 changed files with 8 additions and 8 deletions
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2
arch/arm/include/asm/cacheflush.h
View File

@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
static inline void __flush_icache_all(void)
{
__flush_icache_preferred();
dsb();
dsb(ishst);
}
/*

12
arch/arm/mm/cache-v7.S
View File

@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
bgt 2b
cmp r2, #0
bgt 1b
dsb
dsb st
isb
mov pc, lr
ENDPROC(v7_invalidate_l1)
@ -166,7 +166,7 @@ skip:
finished:
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb
dsb st
isb
mov pc, lr
ENDPROC(v7_flush_dcache_all)
@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
dsb st
mov pc, lr
ENDPROC(v7_flush_kern_dcache_area)
@ -368,7 +368,7 @@ v7_dma_inv_range:
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
dsb st
mov pc, lr
ENDPROC(v7_dma_inv_range)
@ -390,7 +390,7 @@ v7_dma_clean_range:
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
dsb st
mov pc, lr
ENDPROC(v7_dma_clean_range)
@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
dsb st
mov pc, lr
ENDPROC(v7_dma_flush_range)

2
arch/arm/mm/mmu.c
View File

@ -1465,7 +1465,7 @@ void __init early_paging_init(const struct machine_desc *mdesc,
* just complicate the code.
*/
flush_cache_louis();
dsb();
dsb(ishst);
isb();
/* remap level 1 table */