irqchip/gic-v3: Report that effective affinity is a single target
The GICv3 driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-5-marc.zyngier@arm.com
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@ -35,6 +35,7 @@ config ARM_GIC_V3
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select MULTI_IRQ_HANDLER
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select MULTI_IRQ_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_V3_ITS
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config ARM_GIC_V3_ITS
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bool
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bool
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@ -670,6 +670,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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else
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else
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gic_dist_wait_for_rwp();
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gic_dist_wait_for_rwp();
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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return IRQ_SET_MASK_OK_DONE;
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return IRQ_SET_MASK_OK_DONE;
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}
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}
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#else
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#else
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@ -768,6 +770,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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handle_fasteoi_irq, NULL, NULL);
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irq_set_probe(irq);
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irq_set_probe(irq);
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
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}
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}
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/* LPIs */
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/* LPIs */
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if (hw >= 8192 && hw < GIC_ID_NR) {
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if (hw >= 8192 && hw < GIC_ID_NR) {
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