habanalabs: Manipulate DMA addresses in ASIC functions
Routing device accesses to the host memory requires the usage of a base offset, which is canceled by the iATU just before leaving the device. The value of the base offset might be distinctive between different ASIC types. The manipulation of the addresses is currently used throughout the driver code, and one should be aware to it whenever providing a host memory address to the device. This patch removes this manipulation from the driver common code, and moves it to the ASIC specific functions that are responsible for host memory allocation/mapping. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Tomer Tayar
Oded Gabbay
parent
d9c3aa8038
commit
94cb669ceb
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@ -249,8 +249,7 @@ int hl_fw_armcp_info_get(struct hl_device *hdev)
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pkt.ctl = cpu_to_le32(ARMCP_PACKET_INFO_GET <<
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ARMCP_PKT_CTL_OPCODE_SHIFT);
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pkt.addr = cpu_to_le64(armcp_info_dma_addr +
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prop->host_phys_base_address);
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pkt.addr = cpu_to_le64(armcp_info_dma_addr);
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pkt.data_max_size = cpu_to_le32(sizeof(struct armcp_info));
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rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
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@ -281,7 +280,6 @@ out:
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int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct armcp_packet pkt = {};
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void *eeprom_info_cpu_addr;
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dma_addr_t eeprom_info_dma_addr;
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@ -301,8 +299,7 @@ int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size)
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pkt.ctl = cpu_to_le32(ARMCP_PACKET_EEPROM_DATA_GET <<
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ARMCP_PKT_CTL_OPCODE_SHIFT);
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pkt.addr = cpu_to_le64(eeprom_info_dma_addr +
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prop->host_phys_base_address);
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pkt.addr = cpu_to_le64(eeprom_info_dma_addr);
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pkt.data_max_size = cpu_to_le32(max_size);
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rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
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@ -345,7 +345,6 @@ void goya_get_fixed_properties(struct hl_device *hdev)
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prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
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prop->dram_page_size = PAGE_SIZE_2MB;
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prop->host_phys_base_address = HOST_PHYS_BASE;
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prop->va_space_host_start_address = VA_HOST_SPACE_START;
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prop->va_space_host_end_address = VA_HOST_SPACE_END;
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prop->va_space_dram_start_address = VA_DDR_SPACE_START;
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@ -422,7 +421,7 @@ static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
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static int goya_init_iatu(struct hl_device *hdev)
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{
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return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE,
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HOST_PHYS_SIZE);
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HOST_PHYS_BASE, HOST_PHYS_SIZE);
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}
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/*
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@ -804,7 +803,6 @@ void goya_init_dma_qmans(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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struct hl_hw_queue *q;
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dma_addr_t bus_address;
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int i;
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if (goya->hw_cap_initialized & HW_CAP_DMA)
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@ -813,10 +811,7 @@ void goya_init_dma_qmans(struct hl_device *hdev)
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q = &hdev->kernel_queues[0];
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for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
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bus_address = q->bus_address +
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hdev->asic_prop.host_phys_base_address;
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goya_init_dma_qman(hdev, i, bus_address);
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goya_init_dma_qman(hdev, i, q->bus_address);
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goya_init_dma_ch(hdev, i);
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}
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@ -957,7 +952,6 @@ int goya_init_cpu_queues(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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struct hl_eq *eq;
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dma_addr_t bus_address;
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u32 status;
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struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
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int err;
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@ -970,19 +964,18 @@ int goya_init_cpu_queues(struct hl_device *hdev)
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eq = &hdev->event_queue;
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bus_address = cpu_pq->bus_address +
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hdev->asic_prop.host_phys_base_address;
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0, lower_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1, upper_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0,
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lower_32_bits(cpu_pq->bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1,
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upper_32_bits(cpu_pq->bus_address));
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bus_address = eq->bus_address + hdev->asic_prop.host_phys_base_address;
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(eq->bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(eq->bus_address));
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bus_address = hdev->cpu_accessible_dma_address +
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hdev->asic_prop.host_phys_base_address;
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8, lower_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9, upper_32_bits(bus_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8,
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lower_32_bits(hdev->cpu_accessible_dma_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9,
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upper_32_bits(hdev->cpu_accessible_dma_address));
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_5, HL_QUEUE_SIZE_IN_BYTES);
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WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_4, HL_EQ_SIZE_IN_BYTES);
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@ -2731,13 +2724,23 @@ void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val)
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static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
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dma_addr_t *dma_handle, gfp_t flags)
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{
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return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags);
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void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
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dma_handle, flags);
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/* Shift to the device's base physical address of host memory */
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if (kernel_addr)
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*dma_handle += HOST_PHYS_BASE;
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return kernel_addr;
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}
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static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle);
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/* Cancel the device's base physical address of host memory */
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dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
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dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
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}
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void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
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@ -2848,8 +2851,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
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(1 << GOYA_PKT_CTL_MB_SHIFT);
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fence_pkt->ctl = cpu_to_le32(tmp);
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fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
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fence_pkt->addr = cpu_to_le64(fence_dma_addr +
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hdev->asic_prop.host_phys_base_address);
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fence_pkt->addr = cpu_to_le64(fence_dma_addr);
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rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
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job->job_cb_size, cb->bus_address);
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@ -2928,8 +2930,7 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
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(1 << GOYA_PKT_CTL_MB_SHIFT);
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fence_pkt->ctl = cpu_to_le32(tmp);
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fence_pkt->value = cpu_to_le32(fence_val);
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fence_pkt->addr = cpu_to_le64(fence_dma_addr +
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hdev->asic_prop.host_phys_base_address);
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fence_pkt->addr = cpu_to_le64(fence_dma_addr);
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rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
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sizeof(struct packet_msg_prot),
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@ -3001,16 +3002,27 @@ int goya_test_queues(struct hl_device *hdev)
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static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
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gfp_t mem_flags, dma_addr_t *dma_handle)
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{
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void *kernel_addr;
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if (size > GOYA_DMA_POOL_BLK_SIZE)
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return NULL;
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return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
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kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
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/* Shift to the device's base physical address of host memory */
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if (kernel_addr)
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*dma_handle += HOST_PHYS_BASE;
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return kernel_addr;
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}
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static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
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dma_addr_t dma_addr)
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{
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dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
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/* Cancel the device's base physical address of host memory */
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dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
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dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
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}
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void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
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@ -3025,19 +3037,33 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
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}
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static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sg,
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static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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if (!dma_map_sg(&hdev->pdev->dev, sg, nents, dir))
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struct scatterlist *sg;
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int i;
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if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
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return -ENOMEM;
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/* Shift to the device's base physical address of host memory */
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for_each_sg(sgl, sg, nents, i)
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sg->dma_address += HOST_PHYS_BASE;
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return 0;
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}
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static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sg,
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static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir)
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{
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dma_unmap_sg(&hdev->pdev->dev, sg, nents, dir);
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struct scatterlist *sg;
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int i;
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/* Cancel the device's base physical address of host memory */
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for_each_sg(sgl, sg, nents, i)
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sg->dma_address -= HOST_PHYS_BASE;
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dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
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}
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u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
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@ -3589,8 +3615,6 @@ static int goya_patch_dma_packet(struct hl_device *hdev,
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new_dma_pkt->ctl = cpu_to_le32(ctl);
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new_dma_pkt->tsize = cpu_to_le32((u32) len);
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dma_addr += hdev->asic_prop.host_phys_base_address;
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if (dir == DMA_TO_DEVICE) {
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new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
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new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
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@ -135,8 +135,6 @@ enum hl_device_hw_state {
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* @dram_user_base_address: DRAM physical start address for user access.
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* @dram_size: DRAM total size.
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* @dram_pci_bar_size: size of PCI bar towards DRAM.
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* @host_phys_base_address: base physical address of host memory for
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* transactions that the device generates.
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* @max_power_default: max power of the device after reset
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* @va_space_host_start_address: base address of virtual memory range for
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* mapping host memory.
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@ -184,7 +182,6 @@ struct asic_fixed_properties {
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u64 dram_user_base_address;
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u64 dram_size;
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u64 dram_pci_bar_size;
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u64 host_phys_base_address;
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u64 max_power_default;
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u64 va_space_host_start_address;
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u64 va_space_host_end_address;
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@ -537,11 +534,11 @@ struct hl_asic_funcs {
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void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev,
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size_t size, void *vaddr);
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void (*hl_dma_unmap_sg)(struct hl_device *hdev,
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struct scatterlist *sg, int nents,
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struct scatterlist *sgl, int nents,
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enum dma_data_direction dir);
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int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser);
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int (*asic_dma_map_sg)(struct hl_device *hdev,
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struct scatterlist *sg, int nents,
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struct scatterlist *sgl, int nents,
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enum dma_data_direction dir);
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u32 (*get_dma_desc_list_size)(struct hl_device *hdev,
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struct sg_table *sgt);
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@ -1450,7 +1447,8 @@ int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data);
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int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar,
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u64 addr);
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int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address,
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u64 dram_base_address, u64 host_phys_size);
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u64 dram_base_address, u64 host_phys_base_address,
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u64 host_phys_size);
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int hl_pci_init(struct hl_device *hdev, u8 dma_mask);
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void hl_pci_fini(struct hl_device *hdev);
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int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask);
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@ -82,7 +82,7 @@ static void ext_queue_submit_bd(struct hl_device *hdev, struct hl_hw_queue *q,
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bd += hl_pi_2_offset(q->pi);
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bd->ctl = __cpu_to_le32(ctl);
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bd->len = __cpu_to_le32(len);
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bd->ptr = __cpu_to_le64(ptr + hdev->asic_prop.host_phys_base_address);
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bd->ptr = __cpu_to_le64(ptr);
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q->pi = hl_queue_inc_ptr(q->pi);
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hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi);
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@ -263,9 +263,7 @@ static void ext_hw_queue_schedule_job(struct hl_cs_job *job)
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* checked in hl_queue_sanity_checks
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*/
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cq = &hdev->completion_queue[q->hw_queue_id];
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cq_addr = cq->bus_address +
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hdev->asic_prop.host_phys_base_address;
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cq_addr += cq->pi * sizeof(struct hl_cq_entry);
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cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry);
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hdev->asic_funcs->add_end_of_cb_packets(cb->kernel_address, len,
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cq_addr,
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@ -759,10 +759,6 @@ static int map_phys_page_pack(struct hl_ctx *ctx, u64 vaddr,
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for (i = 0 ; i < phys_pg_pack->npages ; i++) {
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paddr = phys_pg_pack->pages[i];
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/* For accessing the host we need to turn on bit 39 */
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if (phys_pg_pack->created_from_userptr)
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paddr += hdev->asic_prop.host_phys_base_address;
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rc = hl_mmu_map(ctx, next_vaddr, paddr, page_size);
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if (rc) {
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dev_err(hdev->dev,
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@ -236,6 +236,8 @@ int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar,
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* @hdev: Pointer to hl_device structure.
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* @sram_base_address: SRAM base address.
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* @dram_base_address: DRAM base address.
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* @host_phys_base_address: Base physical address of host memory for device
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* transactions.
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* @host_phys_size: Size of host memory for device transactions.
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*
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* This is needed in case the firmware doesn't initialize the iATU.
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@ -243,7 +245,8 @@ int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar,
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address,
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u64 dram_base_address, u64 host_phys_size)
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u64 dram_base_address, u64 host_phys_base_address,
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u64 host_phys_size)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 host_phys_end_addr;
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@ -265,11 +268,11 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address,
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/* Outbound Region 0 - Point to Host */
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host_phys_end_addr = prop->host_phys_base_address + host_phys_size - 1;
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host_phys_end_addr = host_phys_base_address + host_phys_size - 1;
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rc |= hl_pci_iatu_write(hdev, 0x008,
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lower_32_bits(prop->host_phys_base_address));
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lower_32_bits(host_phys_base_address));
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rc |= hl_pci_iatu_write(hdev, 0x00C,
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upper_32_bits(prop->host_phys_base_address));
|
||||
upper_32_bits(host_phys_base_address));
|
||||
rc |= hl_pci_iatu_write(hdev, 0x010, lower_32_bits(host_phys_end_addr));
|
||||
rc |= hl_pci_iatu_write(hdev, 0x014, 0);
|
||||
rc |= hl_pci_iatu_write(hdev, 0x018, 0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue