ARM: tegra: apalis-tk1: get rid of fake clocks simple bus

Get rid of the fake clocks simple bus and use node names as per the
actual schematics.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Marcel Ziswiler 2018-09-01 15:05:02 +02:00 committed by Thierry Reding
parent 26e19cdf66
commit 94c3847dc5
2 changed files with 8 additions and 22 deletions

View File

@ -1931,18 +1931,11 @@
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
clk32k_in: osc3 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
cpu@0 {

View File

@ -1961,18 +1961,11 @@
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
clk32k_in: osc3 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
cpu@0 {