amd64_edac: Add Family 16h support
Add code to handle DRAM ECC errors decoding for Fam16h. Tested on Fam16h with ECC turned on using the mce_amd_inj facility and works fine. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Boris: cleanups and clarifications ] Signed-off-by: Borislav Petkov <bp@suse.de>
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@ -20,12 +20,14 @@ const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{}
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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static struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
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{}
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};
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@ -81,7 +83,6 @@ int amd_cache_northbridges(void)
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next_northbridge(link, amd_nb_link_ids);
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_GART;
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@ -98,6 +98,7 @@ int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
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*
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* F15h: we select which DCT we access using F1x10C[DctCfgSel]
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*
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* F16h: has only 1 DCT
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*/
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static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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const char *func)
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@ -340,6 +341,27 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
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base_bits = GENMASK(21, 31) | GENMASK(9, 15);
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mask_bits = GENMASK(21, 29) | GENMASK(9, 15);
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addr_shift = 4;
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/*
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* F16h needs two addr_shift values: 8 for high and 6 for low
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* (cf. F16h BKDG).
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*/
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} else if (boot_cpu_data.x86 == 0x16) {
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csbase = pvt->csels[dct].csbases[csrow];
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csmask = pvt->csels[dct].csmasks[csrow >> 1];
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*base = (csbase & GENMASK(5, 15)) << 6;
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*base |= (csbase & GENMASK(19, 30)) << 8;
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*mask = ~0ULL;
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/* poke holes for the csmask */
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*mask &= ~((GENMASK(5, 15) << 6) |
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(GENMASK(19, 30) << 8));
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*mask |= (csmask & GENMASK(5, 15)) << 6;
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*mask |= (csmask & GENMASK(19, 30)) << 8;
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return;
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} else {
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csbase = pvt->csels[dct].csbases[csrow];
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csmask = pvt->csels[dct].csmasks[csrow >> 1];
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@ -1150,6 +1172,21 @@ static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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return ddr3_cs_size(cs_mode, false);
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}
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/*
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* F16h has only limited cs_modes
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*/
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static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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unsigned cs_mode)
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{
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WARN_ON(cs_mode > 12);
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if (cs_mode == 6 || cs_mode == 8 ||
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cs_mode == 9 || cs_mode == 12)
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return -1;
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else
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return ddr3_cs_size(cs_mode, false);
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}
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static void read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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@ -1587,6 +1624,17 @@ static struct amd64_family_type amd64_family_types[] = {
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.read_dct_pci_cfg = f15_read_dct_pci_cfg,
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}
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},
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[F16_CPUS] = {
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.ctl_name = "F16h",
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.f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
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.f3_id = PCI_DEVICE_ID_AMD_16H_NB_F3,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f16_dbam_to_chip_select,
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.read_dct_pci_cfg = f10_read_dct_pci_cfg,
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}
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},
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};
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/*
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@ -1939,7 +1987,9 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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if (c->x86 >= 0x10) {
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amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
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amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
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if (c->x86 != 0x16)
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/* F16h has only DCT0 */
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amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
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/* F10h, revD and later can do x8 ECC too */
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if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25))
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@ -2356,6 +2406,11 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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pvt->ops = &amd64_family_types[F15_CPUS].ops;
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break;
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case 0x16:
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fam_type = &amd64_family_types[F16_CPUS];
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pvt->ops = &amd64_family_types[F16_CPUS].ops;
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break;
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default:
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amd64_err("Unsupported family!\n");
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return NULL;
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@ -2581,6 +2636,14 @@ static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {
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.class = 0,
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.class_mask = 0,
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},
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{
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_16H_NB_F2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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},
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{0, }
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};
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@ -172,7 +172,8 @@
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*/
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#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
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#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
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#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
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#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
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/*
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* Function 1 - Address Map
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@ -296,6 +297,7 @@ enum amd_families {
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K8_CPUS = 0,
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F10_CPUS,
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F15_CPUS,
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F16_CPUS,
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NUM_FAMILIES,
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};
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@ -524,6 +524,8 @@
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#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
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#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604
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#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605
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#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
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#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
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#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
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