spi: fsl-dspi: Set max_speed_hz for master
Calculate and update max speed from bus clock for SoCs using DSPI IP. The bus clock factor's are taken from the data sheets of respective SoCs. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Mark Brown <broonie@kernel.org>
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c508709bcf
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9419b2006c
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@ -121,18 +121,22 @@ enum dspi_trans_mode {
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struct fsl_dspi_devtype_data {
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enum dspi_trans_mode trans_mode;
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u8 max_clock_factor;
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 2,
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};
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static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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static const struct fsl_dspi_devtype_data ls2085a_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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struct fsl_dspi {
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@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev)
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}
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clk_prepare_enable(dspi->clk);
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master->max_speed_hz =
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clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
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init_waitqueue_head(&dspi->waitq);
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platform_set_drvdata(pdev, master);
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