ALSA: fm801: convert TEA575x support to new interface
Use common functions to access TEA575x tuner - remove original read/write functions and provide new pin manipulation functions instead. Also convert the original triple implementation to a simple GPIO pin map. Tested with SF256-PCP and SF64-PCR (added the GPIO pin for MO/ST signal for them). SF256-PCS untested (pin for MO/ST signal is a guess). Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Ondrej Zary
Takashi Iwai
parent
72587173cc
commit
938a1566b1
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@ -717,308 +717,86 @@ static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pc
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#ifdef TEA575X_RADIO
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/* 256PCS GPIO numbers */
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#define TEA_256PCS_DATA 1
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#define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
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#define TEA_256PCS_BUS_CLOCK 3
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/* GPIO to TEA575x maps */
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struct snd_fm801_tea575x_gpio {
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u8 data, clk, wren, most;
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};
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static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
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static struct snd_fm801_tea575x_gpio snd_fm801_tea575x_gpios[] = {
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{ .data = 1, .clk = 3, .wren = 2, .most = 0 }, /* SF256-PCS */
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{ .data = 1, .clk = 0, .wren = 2, .most = 3 }, /* SF256-PCP */
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{ .data = 2, .clk = 0, .wren = 1, .most = 3 }, /* SF64-PCR */
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};
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static void snd_fm801_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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int i = 25;
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unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL));
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struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1];
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reg &= ~(FM801_GPIO_GP(gpio.data) |
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FM801_GPIO_GP(gpio.clk) |
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FM801_GPIO_GP(gpio.wren));
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reg |= (pins & TEA575X_DATA) ? FM801_GPIO_GP(gpio.data) : 0;
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reg |= (pins & TEA575X_CLK) ? FM801_GPIO_GP(gpio.clk) : 0;
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/* WRITE_ENABLE is inverted */
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reg |= (pins & TEA575X_WREN) ? 0 : FM801_GPIO_GP(gpio.wren);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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}
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static u8 snd_fm801_tea575x_get_pins(struct snd_tea575x *tea)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL));
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struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1];
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return (reg & FM801_GPIO_GP(gpio.data)) ? TEA575X_DATA : 0 |
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(reg & FM801_GPIO_GP(gpio.most)) ? TEA575X_MOST : 0;
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}
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static void snd_fm801_tea575x_set_direction(struct snd_tea575x *tea, bool output)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg = inw(FM801_REG(chip, GPIO_CTRL));
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struct snd_fm801_tea575x_gpio gpio = snd_fm801_tea575x_gpios[(chip->tea575x_tuner & TUNER_TYPE_MASK) - 1];
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines and set write enable bit */
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reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
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FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
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/* all of lines are in the write direction */
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/* clear data and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
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FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCS_DATA) |
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FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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while (i--) {
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if (val & (1 << i))
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reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
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else
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reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GS(gpio.data) |
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FM801_GPIO_GS(gpio.wren) |
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FM801_GPIO_GS(gpio.clk) |
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FM801_GPIO_GS(gpio.most);
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if (output) {
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/* all of lines are in the write direction */
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/* clear data and clock lines */
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reg &= ~(FM801_GPIO_GD(gpio.data) |
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FM801_GPIO_GD(gpio.wren) |
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FM801_GPIO_GD(gpio.clk) |
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FM801_GPIO_GP(gpio.data) |
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FM801_GPIO_GP(gpio.clk) |
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FM801_GPIO_GP(gpio.wren));
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} else {
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/* use GPIO lines, set data direction to input */
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reg |= FM801_GPIO_GD(gpio.data) |
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FM801_GPIO_GD(gpio.most) |
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FM801_GPIO_GP(gpio.data) |
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FM801_GPIO_GP(gpio.most) |
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FM801_GPIO_GP(gpio.wren);
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/* all of lines are in the write direction, except data */
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/* clear data, write enable and clock lines */
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reg &= ~(FM801_GPIO_GD(gpio.wren) |
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FM801_GPIO_GD(gpio.clk) |
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FM801_GPIO_GP(gpio.clk));
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}
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/* and reset the write enable bit */
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reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
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FM801_GPIO_GP(TEA_256PCS_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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spin_unlock_irq(&chip->reg_lock);
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}
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static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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unsigned int val = 0;
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int i;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines, set data direction to input */
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reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
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FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
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FM801_GPIO_GD(TEA_256PCS_DATA) |
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FM801_GPIO_GP(TEA_256PCS_DATA) |
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FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
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/* all of lines are in the write direction, except data */
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/* clear data, write enable and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
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for (i = 0; i < 24; i++) {
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reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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val <<= 1;
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if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
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val |= 1;
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}
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spin_unlock_irq(&chip->reg_lock);
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return val;
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}
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/* 256PCPR GPIO numbers */
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#define TEA_256PCPR_BUS_CLOCK 0
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#define TEA_256PCPR_DATA 1
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#define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
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static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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int i = 25;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines and set write enable bit */
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reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
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FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
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/* all of lines are in the write direction */
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/* clear data and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
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FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCPR_DATA) |
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FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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while (i--) {
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if (val & (1 << i))
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reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
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else
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reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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}
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/* and reset the write enable bit */
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reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
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FM801_GPIO_GP(TEA_256PCPR_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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spin_unlock_irq(&chip->reg_lock);
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}
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static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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unsigned int val = 0;
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int i;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines, set data direction to input */
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reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
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FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
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FM801_GPIO_GD(TEA_256PCPR_DATA) |
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FM801_GPIO_GP(TEA_256PCPR_DATA) |
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FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
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/* all of lines are in the write direction, except data */
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/* clear data, write enable and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
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for (i = 0; i < 24; i++) {
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reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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val <<= 1;
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if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
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val |= 1;
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}
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spin_unlock_irq(&chip->reg_lock);
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return val;
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}
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/* 64PCR GPIO numbers */
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#define TEA_64PCR_BUS_CLOCK 0
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#define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
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#define TEA_64PCR_DATA 2
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static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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int i = 25;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines and set write enable bit */
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reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
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FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
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/* all of lines are in the write direction */
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/* clear data and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
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FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_64PCR_DATA) |
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FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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while (i--) {
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if (val & (1 << i))
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reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
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else
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reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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}
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/* and reset the write enable bit */
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reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
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FM801_GPIO_GP(TEA_64PCR_DATA);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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spin_unlock_irq(&chip->reg_lock);
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}
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static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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unsigned int val = 0;
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int i;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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/* use GPIO lines, set data direction to input */
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reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
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FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
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FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
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FM801_GPIO_GD(TEA_64PCR_DATA) |
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FM801_GPIO_GP(TEA_64PCR_DATA) |
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FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
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/* all of lines are in the write direction, except data */
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/* clear data, write enable and clock lines */
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reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
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FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
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FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
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for (i = 0; i < 24; i++) {
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reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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val <<= 1;
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if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
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val |= 1;
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}
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spin_unlock_irq(&chip->reg_lock);
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return val;
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}
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static void snd_fm801_tea575x_64pcr_mute(struct snd_tea575x *tea,
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unsigned int mute)
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{
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struct fm801 *chip = tea->private_data;
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unsigned short reg;
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spin_lock_irq(&chip->reg_lock);
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reg = inw(FM801_REG(chip, GPIO_CTRL));
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if (mute)
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/* 0xf800 (mute) */
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reg &= ~FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
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else
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/* 0xf802 (unmute) */
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reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
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outw(reg, FM801_REG(chip, GPIO_CTRL));
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udelay(1);
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spin_unlock_irq(&chip->reg_lock);
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}
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static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
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{
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/* 1 = MediaForte 256-PCS */
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.write = snd_fm801_tea575x_256pcs_write,
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.read = snd_fm801_tea575x_256pcs_read,
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},
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{
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/* 2 = MediaForte 256-PCPR */
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.write = snd_fm801_tea575x_256pcpr_write,
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.read = snd_fm801_tea575x_256pcpr_read,
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},
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{
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/* 3 = MediaForte 64-PCR */
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.write = snd_fm801_tea575x_64pcr_write,
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.read = snd_fm801_tea575x_64pcr_read,
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.mute = snd_fm801_tea575x_64pcr_mute,
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}
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static struct snd_tea575x_ops snd_fm801_tea_ops = {
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.set_pins = snd_fm801_tea575x_set_pins,
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.get_pins = snd_fm801_tea575x_get_pins,
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.set_direction = snd_fm801_tea575x_set_direction,
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};
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#endif
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@ -1456,7 +1234,7 @@ static int __devinit snd_fm801_create(struct snd_card *card,
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chip->tea.card = card;
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chip->tea.freq_fixup = 10700;
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chip->tea.private_data = chip;
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chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & TUNER_TYPE_MASK) - 1];
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chip->tea.ops = &snd_fm801_tea_ops;
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snd_tea575x_init(&chip->tea);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue