mfd: Add support for Allwinner SoCs ADC
The Allwinner SoCs all have an ADC that can also act as a touchscreen controller and a thermal sensor. For now, only the ADC and the thermal sensor drivers are probed by the MFD, the touchscreen controller support will be added later. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Quentin Schulz
Lee Jones
parent
7fff7d9b15
commit
937d3a0af5
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@ -40,6 +40,21 @@ config MFD_ACT8945A
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linear regulators, along with a complete ActivePath battery
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charger.
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config MFD_SUN4I_GPADC
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tristate "Allwinner sunxi platforms' GPADC MFD driver"
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select MFD_CORE
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select REGMAP_MMIO
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depends on ARCH_SUNXI || COMPILE_TEST
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help
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Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.
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This driver will only map the hardware interrupt and registers, you
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have to select individual drivers based on this MFD to be able to use
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the ADC or the thermal sensor. This will try to probe the ADC driver
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sun4i-gpadc-iio and the hwmon driver iio_hwmon.
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To compile this driver as a module, choose M here: the module will be
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called sun4i-gpadc.
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config MFD_AS3711
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bool "AMS AS3711"
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select MFD_CORE
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@ -211,3 +211,4 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
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obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o
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@ -0,0 +1,181 @@
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/* ADC MFD core driver for sunxi platforms
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*
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* Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/mfd/sun4i-gpadc.h>
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#define ARCH_SUN4I_A10 0
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#define ARCH_SUN5I_A13 1
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#define ARCH_SUN6I_A31 2
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static struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_FIFO_DATA, "FIFO_DATA_PENDING"),
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DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_TEMP_DATA, "TEMP_DATA_PENDING"),
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};
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static const struct regmap_irq sun4i_gpadc_regmap_irq[] = {
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REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
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SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
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REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
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SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
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};
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static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
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.name = "sun4i_gpadc_irq_chip",
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.status_base = SUN4I_GPADC_INT_FIFOS,
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.ack_base = SUN4I_GPADC_INT_FIFOS,
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.mask_base = SUN4I_GPADC_INT_FIFOC,
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.init_ack_masked = true,
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.mask_invert = true,
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.irqs = sun4i_gpadc_regmap_irq,
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.num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
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.num_regs = 1,
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};
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static struct mfd_cell sun4i_gpadc_cells[] = {
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{
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.name = "sun4i-a10-gpadc-iio",
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.resources = adc_resources,
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.num_resources = ARRAY_SIZE(adc_resources),
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},
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{ .name = "iio_hwmon" }
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};
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static struct mfd_cell sun5i_gpadc_cells[] = {
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{
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.name = "sun5i-a13-gpadc-iio",
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.resources = adc_resources,
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.num_resources = ARRAY_SIZE(adc_resources),
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},
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{ .name = "iio_hwmon" },
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};
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static struct mfd_cell sun6i_gpadc_cells[] = {
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{
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.name = "sun6i-a31-gpadc-iio",
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.resources = adc_resources,
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.num_resources = ARRAY_SIZE(adc_resources),
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},
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{ .name = "iio_hwmon" },
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};
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static const struct regmap_config sun4i_gpadc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.fast_io = true,
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};
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static const struct of_device_id sun4i_gpadc_of_match[] = {
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{
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.compatible = "allwinner,sun4i-a10-ts",
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.data = (void *)ARCH_SUN4I_A10,
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}, {
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.compatible = "allwinner,sun5i-a13-ts",
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.data = (void *)ARCH_SUN5I_A13,
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}, {
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.compatible = "allwinner,sun6i-a31-ts",
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.data = (void *)ARCH_SUN6I_A31,
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}, { /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_match);
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static int sun4i_gpadc_probe(struct platform_device *pdev)
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{
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struct sun4i_gpadc_dev *dev;
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struct resource *mem;
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const struct of_device_id *of_id;
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const struct mfd_cell *cells;
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unsigned int irq, size;
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int ret;
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of_id = of_match_node(sun4i_gpadc_of_match, pdev->dev.of_node);
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if (!of_id)
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return -EINVAL;
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switch ((int)of_id->data) {
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case ARCH_SUN4I_A10:
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cells = sun4i_gpadc_cells;
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size = ARRAY_SIZE(sun4i_gpadc_cells);
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break;
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case ARCH_SUN5I_A13:
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cells = sun5i_gpadc_cells;
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size = ARRAY_SIZE(sun5i_gpadc_cells);
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break;
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case ARCH_SUN6I_A31:
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cells = sun6i_gpadc_cells;
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size = ARRAY_SIZE(sun6i_gpadc_cells);
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break;
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default:
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return -EINVAL;
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}
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dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dev->base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(dev->base))
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return PTR_ERR(dev->base);
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dev->dev = &pdev->dev;
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dev_set_drvdata(dev->dev, dev);
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dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
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&sun4i_gpadc_regmap_config);
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if (IS_ERR(dev->regmap)) {
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ret = PTR_ERR(dev->regmap);
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dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
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return ret;
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}
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/* Disable all interrupts */
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regmap_write(dev->regmap, SUN4I_GPADC_INT_FIFOC, 0);
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irq = platform_get_irq(pdev, 0);
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ret = devm_regmap_add_irq_chip(&pdev->dev, dev->regmap, irq,
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IRQF_ONESHOT, 0,
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&sun4i_gpadc_regmap_irq_chip,
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&dev->regmap_irqc);
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if (ret) {
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dev_err(&pdev->dev, "failed to add irq chip: %d\n", ret);
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return ret;
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}
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ret = devm_mfd_add_devices(dev->dev, 0, cells, size, NULL, 0, NULL);
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if (ret) {
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dev_err(&pdev->dev, "failed to add MFD devices: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static struct platform_driver sun4i_gpadc_driver = {
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.driver = {
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.name = "sun4i-gpadc",
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.of_match_table = of_match_ptr(sun4i_gpadc_of_match),
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},
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.probe = sun4i_gpadc_probe,
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};
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module_platform_driver(sun4i_gpadc_driver);
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MODULE_DESCRIPTION("Allwinner sunxi platforms' GPADC MFD core driver");
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MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,94 @@
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/* Header of ADC MFD core driver for sunxi platforms
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*
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* Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#ifndef __SUN4I_GPADC__H__
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#define __SUN4I_GPADC__H__
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#define SUN4I_GPADC_CTRL0 0x00
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#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
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#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE BIT(23)
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#define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22)
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#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
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#define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
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#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
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#define SUN4I_GPADC_CTRL1 0x04
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#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)
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#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN BIT(9)
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#define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(6)
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#define SUN4I_GPADC_CTRL1_TP_DUAL_EN BIT(5)
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#define SUN4I_GPADC_CTRL1_TP_MODE_EN BIT(4)
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#define SUN4I_GPADC_CTRL1_TP_ADC_SELECT BIT(3)
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#define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
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/* TP_CTRL1 bits for sun6i SOCs */
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#define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(7)
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#define SUN6I_GPADC_CTRL1_TP_DUAL_EN BIT(6)
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#define SUN6I_GPADC_CTRL1_TP_MODE_EN BIT(5)
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#define SUN6I_GPADC_CTRL1_TP_ADC_SELECT BIT(4)
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#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
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#define SUN4I_GPADC_CTRL2 0x08
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#define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)
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#define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26)
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#define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24)
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#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
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#define SUN4I_GPADC_CTRL3 0x0c
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#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
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#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
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#define SUN4I_GPADC_TPR 0x18
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#define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16)
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#define SUN4I_GPADC_TPR_TEMP_PERIOD(x) (GENMASK(15, 0) & (x))
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#define SUN4I_GPADC_INT_FIFOC 0x10
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#define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN BIT(18)
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#define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN BIT(17)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN BIT(16)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE BIT(13)
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#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN BIT(7)
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#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH BIT(4)
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#define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1)
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#define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
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#define SUN4I_GPADC_INT_FIFOS 0x14
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#define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
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#define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING BIT(17)
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#define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING BIT(16)
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#define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG BIT(2)
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#define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1)
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#define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0)
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#define SUN4I_GPADC_CDAT 0x1c
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#define SUN4I_GPADC_TEMP_DATA 0x20
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#define SUN4I_GPADC_DATA 0x24
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#define SUN4I_GPADC_IRQ_FIFO_DATA 0
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#define SUN4I_GPADC_IRQ_TEMP_DATA 1
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/* 10s delay before suspending the IP */
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#define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000
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struct sun4i_gpadc_dev {
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *regmap_irqc;
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void __iomem *base;
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};
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#endif
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