MIPS: Lantiq: Add more gpio drivers
The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only. [ralf@linux-mips.org: Fixed ltq_stp_probe section() attributes.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2258/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
973c32eb7f
commit
935c500c37
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@ -1,4 +1,4 @@
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obj-y := pmu.o ebu.o reset.o gpio.o devices.o
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obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o
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obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
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obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
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@ -0,0 +1,126 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <lantiq_soc.h>
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/*
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* By attaching hardware latches to the EBU it is possible to create output
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* only gpios. This driver configures a special memory address, which when
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* written to outputs 16 bit to the latches.
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*/
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#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */
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#define LTQ_EBU_WP 0x80000000 /* write protect bit */
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/* we keep a shadow value of the last value written to the ebu */
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static int ltq_ebu_gpio_shadow = 0x0;
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static void __iomem *ltq_ebu_gpio_membase;
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static void ltq_ebu_apply(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&ebu_lock, flags);
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ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
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*((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
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ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
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spin_unlock_irqrestore(&ebu_lock, flags);
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}
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static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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if (value)
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ltq_ebu_gpio_shadow |= (1 << offset);
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else
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ltq_ebu_gpio_shadow &= ~(1 << offset);
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ltq_ebu_apply();
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}
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static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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ltq_ebu_set(chip, offset, value);
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return 0;
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}
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static struct gpio_chip ltq_ebu_chip = {
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.label = "ltq_ebu",
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.direction_output = ltq_ebu_direction_output,
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.set = ltq_ebu_set,
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.base = 72,
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.ngpio = 16,
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.can_sleep = 1,
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.owner = THIS_MODULE,
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};
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static int ltq_ebu_probe(struct platform_device *pdev)
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{
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int ret = 0;
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get memory resource\n");
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return -ENOENT;
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}
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res = devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), dev_name(&pdev->dev));
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if (!res) {
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dev_err(&pdev->dev, "failed to request memory resource\n");
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return -EBUSY;
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}
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ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!ltq_ebu_gpio_membase) {
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dev_err(&pdev->dev, "Failed to ioremap mem region\n");
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return -ENOMEM;
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}
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/* grab the default shadow value passed form the platform code */
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ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
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/* tell the ebu controller which memory address we will be using */
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ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
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/* write protect the region */
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ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
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ret = gpiochip_add(<q_ebu_chip);
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if (!ret)
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ltq_ebu_apply();
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return ret;
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}
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static struct platform_driver ltq_ebu_driver = {
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.probe = ltq_ebu_probe,
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.driver = {
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.name = "ltq_ebu",
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.owner = THIS_MODULE,
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},
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};
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static int __init ltq_ebu_init(void)
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{
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int ret = platform_driver_register(<q_ebu_driver);
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if (ret)
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pr_info("ltq_ebu : Error registering platfom driver!");
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return ret;
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}
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postcore_initcall(ltq_ebu_init);
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@ -0,0 +1,157 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <lantiq_soc.h>
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#define LTQ_STP_CON0 0x00
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#define LTQ_STP_CON1 0x04
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#define LTQ_STP_CPU0 0x08
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#define LTQ_STP_CPU1 0x0C
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#define LTQ_STP_AR 0x10
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#define LTQ_STP_CON_SWU (1 << 31)
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#define LTQ_STP_2HZ 0
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#define LTQ_STP_4HZ (1 << 23)
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#define LTQ_STP_8HZ (2 << 23)
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#define LTQ_STP_10HZ (3 << 23)
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#define LTQ_STP_SPEED_MASK (0xf << 23)
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#define LTQ_STP_UPD_FPI (1 << 31)
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#define LTQ_STP_UPD_MASK (3 << 30)
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#define LTQ_STP_ADSL_SRC (3 << 24)
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#define LTQ_STP_GROUP0 (1 << 0)
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#define LTQ_STP_RISING 0
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#define LTQ_STP_FALLING (1 << 26)
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#define LTQ_STP_EDGE_MASK (1 << 26)
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#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg)
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#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg)
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#define ltq_stp_w32_mask(clear, set, reg) \
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ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
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ltq_stp_membase + (reg))
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static int ltq_stp_shadow = 0xffff;
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static void __iomem *ltq_stp_membase;
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static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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if (value)
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ltq_stp_shadow |= (1 << offset);
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else
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ltq_stp_shadow &= ~(1 << offset);
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ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
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}
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static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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ltq_stp_set(chip, offset, value);
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return 0;
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}
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static struct gpio_chip ltq_stp_chip = {
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.label = "ltq_stp",
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.direction_output = ltq_stp_direction_output,
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.set = ltq_stp_set,
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.base = 48,
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.ngpio = 24,
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.can_sleep = 1,
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.owner = THIS_MODULE,
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};
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static int ltq_stp_hw_init(void)
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{
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/* the 3 pins used to control the external stp */
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ltq_gpio_request(4, 1, 0, 1, "stp-st");
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ltq_gpio_request(5, 1, 0, 1, "stp-d");
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ltq_gpio_request(6, 1, 0, 1, "stp-sh");
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/* sane defaults */
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ltq_stp_w32(0, LTQ_STP_AR);
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ltq_stp_w32(0, LTQ_STP_CPU0);
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ltq_stp_w32(0, LTQ_STP_CPU1);
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ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
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ltq_stp_w32(0, LTQ_STP_CON1);
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/* rising or falling edge */
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ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
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/* per default stp 15-0 are set */
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ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
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/* stp are update periodically by the FPI bus */
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ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
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/* set stp update speed */
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ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
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/* tell the hardware that pin (led) 0 and 1 are controlled
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* by the dsl arc
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*/
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ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
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ltq_pmu_enable(PMU_LED);
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return 0;
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}
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static int __devinit ltq_stp_probe(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int ret = 0;
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if (!res)
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return -ENOENT;
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res = devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), dev_name(&pdev->dev));
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if (!res) {
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dev_err(&pdev->dev, "failed to request STP memory\n");
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return -EBUSY;
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}
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ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!ltq_stp_membase) {
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dev_err(&pdev->dev, "failed to remap STP memory\n");
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return -ENOMEM;
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}
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ret = gpiochip_add(<q_stp_chip);
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if (!ret)
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ret = ltq_stp_hw_init();
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return ret;
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}
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static struct platform_driver ltq_stp_driver = {
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.probe = ltq_stp_probe,
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.driver = {
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.name = "ltq_stp",
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.owner = THIS_MODULE,
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},
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};
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int __init ltq_stp_init(void)
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{
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int ret = platform_driver_register(<q_stp_driver);
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if (ret)
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pr_info("ltq_stp: error registering platfom driver");
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return ret;
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}
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postcore_initcall(ltq_stp_init);
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