MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions
MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras
parent
8716a76356
commit
934c79231c
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@ -14,6 +14,7 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/mipsmtregs.h>
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@ -39,7 +40,7 @@ extern void (*r4k_blast_icache)(void);
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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@ -147,7 +148,7 @@ static inline void flush_scache_line(unsigned long addr)
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"1: cache %0, (%1) \n" \
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"2: .set pop \n" \
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" .section __ex_table,\"a\" \n" \
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@ -218,6 +219,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
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cache_op(Page_Invalidate_T, addr);
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}
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#ifndef CONFIG_CPU_MIPSR6
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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@ -322,6 +324,150 @@ static inline void invalidate_tcache_page(unsigned long addr)
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: "r" (base), \
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"i" (op));
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#else
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/*
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* MIPS R6 changed the cache opcode and moved to a 8-bit offset field.
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* This means we now need to increment the base register before we flush
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* more cache lines
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*/
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64r6\n" \
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" .set noat\n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0)\n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0)\n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0)\n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0)\n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0)\n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \
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" addiu $1, $0, 0x100 \n" \
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" cache %1, 0x000($1); cache %1, 0x010($1)\n" \
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" cache %1, 0x020($1); cache %1, 0x030($1)\n" \
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" cache %1, 0x040($1); cache %1, 0x050($1)\n" \
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" cache %1, 0x060($1); cache %1, 0x070($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x090($1)\n" \
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" cache %1, 0x0a0($1); cache %1, 0x0b0($1)\n" \
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" cache %1, 0x0c0($1); cache %1, 0x0d0($1)\n" \
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" cache %1, 0x0e0($1); cache %1, 0x0f0($1)\n" \
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" .set pop\n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache32_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64r6\n" \
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" .set noat\n" \
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" cache %1, 0x000(%0); cache %1, 0x020(%0)\n" \
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" cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \
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" cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
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" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
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" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
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" addiu $1, $1, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
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" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
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" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
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" addiu $1, $1, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
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" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
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" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
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" .set pop\n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache64_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64r6\n" \
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" .set noat\n" \
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" cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \
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" cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
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" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
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" .set pop\n" \
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: \
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: "r" (base), \
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"i" (op));
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#define cache128_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noreorder\n" \
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" .set mips64r6\n" \
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" .set noat\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
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" addiu $1, %0, 0x100\n" \
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" .set pop\n" \
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: \
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: "r" (base), \
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"i" (op));
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#endif /* CONFIG_CPU_MIPSR6 */
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/*
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* Perform the cache operation specified by op using a user mode virtual
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* address while in kernel mode.
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