m68knommu: fix 5307 ColdFire UART vector setup
There is a couple of problems with the UART vector setup for the 5307 ColdFire UART. The ICR register access should be 8bit, not 32bit. The address of the UIVR register is wrong, it needs to be offset into the MBAR register region. Fix these. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
parent
d62db60659
commit
9242ef12f0
|
@ -65,12 +65,12 @@ static struct platform_device *m5307_devices[] __initdata = {
|
|||
static void __init m5307_uart_init_line(int line, int irq)
|
||||
{
|
||||
if (line == 0) {
|
||||
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
|
||||
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
|
||||
writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
|
||||
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
|
||||
} else if (line == 1) {
|
||||
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
|
||||
writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
|
||||
writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
|
||||
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue