sh: get rid of div4 clock name
Remove the name parameter from SH_CLK_DIV4() and adjust the processor specific code. The lookup happens using clkdev so the name is unused. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
1fe3d19883
commit
914ebf0bbb
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@ -126,14 +126,13 @@ int clk_rate_table_find(struct clk *clk,
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int sh_clk_mstp32_register(struct clk *clks, int nr);
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#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
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{ \
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.name = _name, \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.enable_bit = _shift, \
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.arch_flags = _div_bitmap, \
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.flags = _flags, \
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#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.enable_bit = _shift, \
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.arch_flags = _div_bitmap, \
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.flags = _flags, \
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}
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struct clk_div4_table {
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@ -122,18 +122,18 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
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DIV4_SIUA, DIV4_SIUB, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
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[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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};
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enum { DIV6_V, DIV6_NR };
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@ -125,18 +125,18 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
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DIV4_SIUA, DIV4_SIUB, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
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[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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};
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enum { DIV6_V, DIV6_NR };
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@ -122,31 +122,31 @@ static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
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[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
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};
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enum { DIV4_IRDA, DIV4_ENABLE_NR };
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struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
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[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
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[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
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};
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enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
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struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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};
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enum { DIV6_V, DIV6_NR };
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@ -125,29 +125,29 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
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[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
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};
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enum { DIV4_IRDA, DIV4_ENABLE_NR };
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struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
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[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
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[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
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};
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enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
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struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
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};
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enum { DIV6_V, DIV6_NR };
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@ -153,15 +153,15 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
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[DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
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[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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};
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enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
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@ -70,18 +70,18 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
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DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_str, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
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#define DIV4(_bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
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[DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
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[DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
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[DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(0, 0x0f80, 0),
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[DIV4_DU] = DIV4(4, 0x0ff0, 0),
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[DIV4_GA] = DIV4(8, 0x0030, 0),
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[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc80030
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@ -72,16 +72,16 @@ static struct clk_div4_table div4_table = {
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_str, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
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#define DIV4(_bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
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[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
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[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(0, 0x0b40, 0),
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[DIV4_DU] = DIV4(4, 0x0010, 0),
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[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc40030
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