cxl/region: Move HPA setup to cxl_region_attach()
A recent bug fix added the setup of the endpoint decoder interleave geometry settings to cxl_region_attach(). Move the HPA setup there as well to keep all endpoint decoder parameter setting in a central location. For symmetry, move endpoint HPA teardown to cxl_region_detach(), and for switches move HPA setup / teardown to cxl_port_{setup,reset}_targets(). Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/165973126020.1526540.14701949254436069807.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -499,28 +499,6 @@ static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl)
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CXL_HDM_DECODER0_CTRL_TYPE);
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}
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static void cxld_set_hpa(struct cxl_decoder *cxld, u64 *base, u64 *size)
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{
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struct cxl_region *cxlr = cxld->region;
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struct cxl_region_params *p = &cxlr->params;
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cxld->hpa_range = (struct range) {
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.start = p->res->start,
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.end = p->res->end,
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};
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*base = p->res->start;
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*size = resource_size(p->res);
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}
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static void cxld_clear_hpa(struct cxl_decoder *cxld)
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{
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cxld->hpa_range = (struct range) {
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.start = 0,
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.end = -1,
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};
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}
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static int cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)
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{
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struct cxl_dport **t = &cxlsd->target[0];
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@ -601,7 +579,8 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld)
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ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
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cxld_set_interleave(cxld, &ctrl);
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cxld_set_type(cxld, &ctrl);
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cxld_set_hpa(cxld, &base, &size);
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base = cxld->hpa_range.start;
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size = range_len(&cxld->hpa_range);
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writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
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writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
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@ -674,7 +653,6 @@ static int cxl_decoder_reset(struct cxl_decoder *cxld)
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ctrl &= ~CXL_HDM_DECODER0_CTRL_COMMIT;
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writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
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cxld_clear_hpa(cxld);
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writel(0, hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id));
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writel(0, hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
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writel(0, hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
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@ -1044,6 +1044,10 @@ static int cxl_port_setup_targets(struct cxl_port *port,
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cxld->interleave_ways = iw;
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cxld->interleave_granularity = ig;
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cxld->hpa_range = (struct range) {
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.start = p->res->start,
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.end = p->res->end,
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};
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dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport),
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dev_name(&port->dev), iw, ig);
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add_target:
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@ -1070,13 +1074,21 @@ static void cxl_port_reset_targets(struct cxl_port *port,
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struct cxl_region *cxlr)
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{
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struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
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struct cxl_decoder *cxld;
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/*
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* After the last endpoint has been detached the entire cxl_rr may now
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* be gone.
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*/
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if (cxl_rr)
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if (!cxl_rr)
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return;
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cxl_rr->nr_targets_set = 0;
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cxld = cxl_rr->decoder;
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cxld->hpa_range = (struct range) {
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.start = 0,
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.end = -1,
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};
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}
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static void cxl_region_teardown_targets(struct cxl_region *cxlr)
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@ -1257,6 +1269,10 @@ static int cxl_region_attach(struct cxl_region *cxlr,
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cxled->cxld.interleave_ways = p->interleave_ways;
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cxled->cxld.interleave_granularity = p->interleave_granularity;
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cxled->cxld.hpa_range = (struct range) {
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.start = p->res->start,
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.end = p->res->end,
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};
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return 0;
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@ -1315,6 +1331,10 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled)
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}
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p->targets[cxled->pos] = NULL;
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p->nr_targets--;
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cxled->cxld.hpa_range = (struct range) {
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.start = 0,
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.end = -1,
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};
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/* notify the region driver that one of its targets has departed */
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up_write(&cxl_region_rwsem);
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