staging: fbtft: add fb_s6d02a1 driver
This commit adds the fb_s6d02a1 driver from the fbtft project at https://github.com/notro/fbtft. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Noralf Tronnes <notro@tronnes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thomas Petazzoni
Greg Kroah-Hartman
parent
d8a53a9d0b
commit
910968f712
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@ -85,3 +85,9 @@ config FB_TFT_RA8875
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depends on FB_TFT
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help
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Generic Framebuffer support for RA8875
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config FB_TFT_S6D02A1
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tristate "FB driver for the S6D02A1 LCD Controller"
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depends on FB_TFT
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help
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Generic Framebuffer support for S6D02A1
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@ -16,3 +16,4 @@ obj-$(CONFIG_FB_TFT_ILI9481) += fb_ili9481.o
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obj-$(CONFIG_FB_TFT_ILI9486) += fb_ili9486.o
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obj-$(CONFIG_FB_TFT_PCD8544) += fb_pcd8544.o
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obj-$(CONFIG_FB_TFT_RA8875) += fb_ra8875.o
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obj-$(CONFIG_FB_TFT_S6D02A1) += fb_s6d02a1.o
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@ -0,0 +1,168 @@
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/*
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* FB driver for the S6D02A1 LCD Controller
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*
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* Based on fb_st7735r.c by Noralf Tronnes
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* Init code from UTFT library by Henning Karlsen
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include "fbtft.h"
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#define DRVNAME "fb_s6d02a1"
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static int default_init_sequence[] = {
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-1, 0xf0, 0x5a, 0x5a,
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-1, 0xfc, 0x5a, 0x5a,
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-1, 0xfa, 0x02, 0x1f, 0x00, 0x10, 0x22, 0x30, 0x38, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A, 0x3d, 0x02, 0x01,
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-1, 0xfb, 0x21, 0x00, 0x02, 0x04, 0x07, 0x0a, 0x0b, 0x0c, 0x0c, 0x16, 0x1e, 0x30, 0x3f, 0x01, 0x02,
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/* power setting sequence */
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-1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x01, 0x01, 0x00, 0x1f, 0x1f,
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-1, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
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-1, 0xf5, 0x00, 0x70, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x66, 0x06,
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-1, 0xf6, 0x02, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x06, 0x01, 0x00,
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-1, 0xf2, 0x00, 0x01, 0x03, 0x08, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x08, 0x08,
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-1, 0xf8, 0x11,
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-1, 0xf7, 0xc8, 0x20, 0x00, 0x00,
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-1, 0xf3, 0x00, 0x00,
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-1, 0x11,
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-2, 50,
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-1, 0xf3, 0x00, 0x01,
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-2, 50,
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-1, 0xf3, 0x00, 0x03,
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-2, 50,
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-1, 0xf3, 0x00, 0x07,
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-2, 50,
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-1, 0xf3, 0x00, 0x0f,
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-2, 50,
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-1, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
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-2, 50,
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-1, 0xf3, 0x00, 0x1f,
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-2, 50,
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-1, 0xf3, 0x00, 0x7f,
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-2, 50,
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-1, 0xf3, 0x00, 0xff,
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-2, 50,
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-1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x00, 0x01, 0x00, 0x16, 0x16,
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-1, 0xf4, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
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/* initializing sequence */
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-1, 0x36, 0x08,
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-1, 0x35, 0x00,
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-1, 0x3a, 0x05,
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/* gamma setting sequence */
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-1, 0x26, 0x01, /* preset gamma curves, possible values 0x01, 0x02, 0x04, 0x08 */
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-2, 150,
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-1, 0x29,
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-1, 0x2c,
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/* end marker */
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-3
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};
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
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"%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
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/* Column address */
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write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
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/* Row adress */
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write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
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/* Memory write */
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write_reg(par, 0x2C);
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}
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#define MY (1 << 7)
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#define MX (1 << 6)
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#define MV (1 << 5)
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static int set_var(struct fbtft_par *par)
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{
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
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/* MADCTL - Memory data access control
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RGB/BGR:
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1. Mode selection pin SRGB
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RGB H/W pin for color filter setting: 0=RGB, 1=BGR
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2. MADCTL RGB bit
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RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */
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switch (par->info->var.rotate) {
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case 0:
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write_reg(par, 0x36, MX | MY | (par->bgr << 3));
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break;
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case 270:
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write_reg(par, 0x36, MY | MV | (par->bgr << 3));
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break;
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case 180:
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write_reg(par, 0x36, (par->bgr << 3));
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break;
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case 90:
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write_reg(par, 0x36, MX | MV | (par->bgr << 3));
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break;
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}
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return 0;
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}
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static struct fbtft_display display = {
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.regwidth = 8,
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.width = 128,
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.height = 160,
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.init_sequence = default_init_sequence,
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.fbtftops = {
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:s6d02a1");
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MODULE_ALIAS("platform:s6d02a1");
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MODULE_DESCRIPTION("FB driver for the S6D02A1 LCD Controller");
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MODULE_AUTHOR("WOLFGANG BUENING");
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MODULE_LICENSE("GPL");
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