iommu/vt-d: Implement deferred invalidate for SVM
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -4981,6 +4981,8 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
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ctx_lo |= CONTEXT_TT_PT_PASID << 2;
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}
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ctx_lo |= CONTEXT_PASIDE;
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if (iommu->pasid_state_table)
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ctx_lo |= CONTEXT_DINVE;
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context[0].lo = ctx_lo;
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wmb();
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iommu->flush.flush_context(iommu, sdev->did, sdev->sid,
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@ -26,6 +26,10 @@ struct pasid_entry {
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u64 val;
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};
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struct pasid_state_entry {
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u64 val;
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};
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int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
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{
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struct page *pages;
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@ -127,6 +131,11 @@ static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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{
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struct intel_svm_dev *sdev;
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/* Try deferred invalidate if available */
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if (svm->iommu->pasid_state_table &&
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!cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
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return;
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
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@ -25,6 +25,7 @@
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#define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
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#define CONTEXT_TT_MASK (7ULL << 2)
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#define CONTEXT_DINVE (1ULL << 8)
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#define CONTEXT_PRS (1ULL << 9)
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#define CONTEXT_PASIDE (1ULL << 11)
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