mtd: nand: sunxi: switch from manual to automated timing config
The NAND framework is now able to select the best NAND timings for us. All we have to do is implement a ->setup_data_interface() function to apply those timings and remove the timing selection code from the sunxi driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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@ -1572,14 +1572,22 @@ static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
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#define sunxi_nand_lookup_timing(l, p, c) \
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_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
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static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
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const struct nand_sdr_timings *timings)
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static int sunxi_nfc_setup_data_interface(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct sunxi_nand_chip *chip = to_sunxi_nand(nand);
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struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
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const struct nand_sdr_timings *timings;
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u32 min_clk_period = 0;
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s32 tWB, tADL, tWHR, tRHW, tCAD;
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long real_clk_rate;
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timings = nand_get_sdr_timings(conf);
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if (IS_ERR(timings))
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return -ENOTSUPP;
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/* T1 <=> tCLS */
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if (timings->tCLS_min > min_clk_period)
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min_clk_period = timings->tCLS_min;
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@ -1679,6 +1687,9 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
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return tRHW;
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}
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if (check_only)
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return 0;
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/*
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* TODO: according to ONFI specs this value only applies for DDR NAND,
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* but Allwinner seems to set this to 0x7. Mimic them for now.
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@ -1712,44 +1723,6 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
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return 0;
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}
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static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
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struct device_node *np)
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{
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struct mtd_info *mtd = nand_to_mtd(&chip->nand);
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const struct nand_sdr_timings *timings;
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int ret;
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int mode;
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mode = onfi_get_async_timing_mode(&chip->nand);
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if (mode == ONFI_TIMING_MODE_UNKNOWN) {
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mode = chip->nand.onfi_timing_mode_default;
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} else {
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uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
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int i;
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mode = fls(mode) - 1;
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if (mode < 0)
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mode = 0;
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feature[0] = mode;
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for (i = 0; i < chip->nsels; i++) {
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chip->nand.select_chip(mtd, i);
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ret = chip->nand.onfi_set_features(mtd, &chip->nand,
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ONFI_FEATURE_ADDR_TIMING_MODE,
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feature);
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chip->nand.select_chip(mtd, -1);
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if (ret)
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return ret;
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}
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}
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timings = onfi_async_timing_mode_to_sdr_timings(mode);
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if (IS_ERR(timings))
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return PTR_ERR(timings);
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return sunxi_nand_chip_set_timings(chip, timings);
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}
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static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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@ -1975,7 +1948,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
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static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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struct device_node *np)
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{
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const struct nand_sdr_timings *timings;
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struct sunxi_nand_chip *chip;
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struct mtd_info *mtd;
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struct nand_chip *nand;
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@ -2065,25 +2037,11 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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nand->read_buf = sunxi_nfc_read_buf;
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nand->write_buf = sunxi_nfc_write_buf;
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nand->read_byte = sunxi_nfc_read_byte;
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nand->setup_data_interface = sunxi_nfc_setup_data_interface;
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mtd = nand_to_mtd(nand);
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mtd->dev.parent = dev;
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timings = onfi_async_timing_mode_to_sdr_timings(0);
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if (IS_ERR(timings)) {
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ret = PTR_ERR(timings);
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dev_err(dev,
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"could not retrieve timings for ONFI mode 0: %d\n",
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ret);
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return ret;
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}
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ret = sunxi_nand_chip_set_timings(chip, timings);
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if (ret) {
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dev_err(dev, "could not configure chip timings: %d\n", ret);
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return ret;
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}
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ret = nand_scan_ident(mtd, nsels, NULL);
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if (ret)
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return ret;
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@ -2096,12 +2054,6 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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nand->options |= NAND_SUBPAGE_READ;
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ret = sunxi_nand_chip_init_timings(chip, np);
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if (ret) {
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dev_err(dev, "could not configure chip timings: %d\n", ret);
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return ret;
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}
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ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
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if (ret) {
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dev_err(dev, "ECC init failed: %d\n", ret);
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