arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
Add basic dts support for i.MX8MQ NITROGEN8M. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> [Dafna: porting vendor's code to mainline] Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Gary Bisson
Shawn Guo
parent
34a33ba609
commit
90771e50d5
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@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
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@ -0,0 +1,405 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018 Boundary Devices
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "imx8mq.dtsi"
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/ {
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model = "Boundary Devices i.MX8MQ Nitrogen8M";
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compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_keys>;
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power {
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label = "Power Button";
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gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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wakeup-source;
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};
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};
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reg_vref_0v9: regulator-vref-0v9 {
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compatible = "regulator-fixed";
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regulator-name = "vref-0v9";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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};
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reg_vref_1v8: regulator-vref-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vref-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_vref_2v5: regulator-vref-2v5 {
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compatible = "regulator-fixed";
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regulator-name = "vref-2v5";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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reg_vref_3v3: regulator-vref-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vref-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_vref_5v: regulator-vref-5v {
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compatible = "regulator-fixed";
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regulator-name = "vref-5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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i2cmux@70 {
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compatible = "nxp,pca9546";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_pca9546>;
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reg = <0x70>;
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reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c1a: i2c1@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_arm_dram: regulator@60 {
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compatible = "fcs,fan53555";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_arm_dram>;
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reg = <0x60>;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
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};
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};
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i2c1b: i2c1@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_dram_1p1v: regulator@60 {
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compatible = "fcs,fan53555";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
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reg = <0x60>;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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};
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};
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i2c1c: i2c1@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_soc_gpu_vpu: regulator@60 {
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compatible = "fcs,fan53555";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
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reg = <0x60>;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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};
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};
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i2c1d: i2c1@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "microcrystal,rv4162";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
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reg = <0x68>;
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interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
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wakeup-source;
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};
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};
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};
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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&usdhc1 {
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bus-width = <8>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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non-removable;
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vmmc-supply = <®_vref_1v8>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* J17 connector, odd */
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MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
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MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
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MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
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MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
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MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
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MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
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MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
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MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
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MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
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MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
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MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
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MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
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MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
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MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
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MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
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MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
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/* J17 connector, even */
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MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
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MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
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MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
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MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
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MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
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/* J18 connector, odd */
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MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
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MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
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MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
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MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
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MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
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MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
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/* J18 connector, even */
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MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
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MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
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MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
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MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
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MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
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MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
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MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
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/* J13 Pin 2, WL_WAKE */
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MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
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/* J13 Pin 4, WL_IRQ, not needed for Silex */
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MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
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/* J13 pin 9, unused */
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
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/* J13 Pin 41, BT_CLK_REQ */
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MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
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/* J13 Pin 42, BT_HOST_WAKE */
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MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
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/* Clock for both CSI1 and CSI2 */
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MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
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/* test points */
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MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
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>;
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};
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pinctrl_gpio_keys: gpio-keysgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c1_pca9546: i2c1-pca9546grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
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>;
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};
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pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
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>;
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};
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pinctrl_reg_arm_dram: reg-arm-dramgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
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>;
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};
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pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
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>;
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};
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pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
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MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
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||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue