drm/mediatek: Add HDMI support
This patch adds drivers for the HDMI bridge connected to the DPI0 display subsystem function block, for the HDMI DDC block, and for the HDMI PHY to support HDMI output. This includes an interface to the generic hdmi-codec driver to start or stop audio playback and to retrieve ELD (EDID like data) to limit the supported audio formats to the HDMI sink capabilities. Signed-off-by: Jie Qiu <jie.qiu@mediatek.com> Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Jie Qiu
Philipp Zabel
parent
7cdeb24db4
commit
8f83f26891
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@ -14,3 +14,11 @@ config DRM_MEDIATEK
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The module will be called mediatek-drm
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This driver provides kernel mode setting and
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buffer management to userspace.
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config DRM_MEDIATEK_HDMI
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tristate "DRM HDMI Support for Mediatek SoCs"
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depends on DRM_MEDIATEK
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select SND_SOC_HDMI_CODEC if SND_SOC
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select GENERIC_PHY
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help
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DRM/KMS HDMI driver for Mediatek SoCs
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@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \
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mtk_dpi.o
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obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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mediatek-drm-hdmi-objs := mtk_cec.o \
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mtk_hdmi.o \
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mtk_hdmi_ddc.o \
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mtk_mt8173_hdmi_phy.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include "mtk_cec.h"
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#define TR_CONFIG 0x00
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#define CLEAR_CEC_IRQ BIT(15)
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#define CEC_CKGEN 0x04
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#define CEC_32K_PDN BIT(19)
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#define PDN BIT(16)
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#define RX_EVENT 0x54
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#define HDMI_PORD BIT(25)
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#define HDMI_HTPLG BIT(24)
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#define HDMI_PORD_INT_EN BIT(9)
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#define HDMI_HTPLG_INT_EN BIT(8)
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#define RX_GEN_WD 0x58
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#define HDMI_PORD_INT_32K_STATUS BIT(26)
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#define RX_RISC_INT_32K_STATUS BIT(25)
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#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
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#define HDMI_PORD_INT_32K_CLR BIT(18)
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#define RX_INT_32K_CLR BIT(17)
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#define HDMI_HTPLG_INT_32K_CLR BIT(16)
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#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
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#define RX_RISC_INT_32K_STA_MASK BIT(9)
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#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
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#define HDMI_PORD_INT_32K_EN BIT(2)
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#define RX_INT_32K_EN BIT(1)
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#define HDMI_HTPLG_INT_32K_EN BIT(0)
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#define NORMAL_INT_CTRL 0x5C
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#define HDMI_HTPLG_INT_STA BIT(0)
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#define HDMI_PORD_INT_STA BIT(1)
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#define HDMI_HTPLG_INT_CLR BIT(16)
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#define HDMI_PORD_INT_CLR BIT(17)
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#define HDMI_FULL_INT_CLR BIT(20)
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struct mtk_cec {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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bool hpd;
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void (*hpd_event)(bool hpd, struct device *dev);
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struct device *hdmi_dev;
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spinlock_t lock;
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};
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static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
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unsigned int bits)
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{
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void __iomem *reg = cec->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp &= ~bits;
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writel(tmp, reg);
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}
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static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
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unsigned int bits)
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{
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void __iomem *reg = cec->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp |= bits;
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writel(tmp, reg);
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}
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static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
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unsigned int val, unsigned int mask)
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{
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u32 tmp = readl(cec->regs + offset) & ~mask;
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tmp |= val & mask;
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writel(val, cec->regs + offset);
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}
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void mtk_cec_set_hpd_event(struct device *dev,
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void (*hpd_event)(bool hpd, struct device *dev),
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struct device *hdmi_dev)
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{
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struct mtk_cec *cec = dev_get_drvdata(dev);
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unsigned long flags;
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spin_lock_irqsave(&cec->lock, flags);
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cec->hdmi_dev = hdmi_dev;
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cec->hpd_event = hpd_event;
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spin_unlock_irqrestore(&cec->lock, flags);
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}
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bool mtk_cec_hpd_high(struct device *dev)
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{
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struct mtk_cec *cec = dev_get_drvdata(dev);
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unsigned int status;
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status = readl(cec->regs + RX_EVENT);
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return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
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}
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static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
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{
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mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
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mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
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RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
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mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
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HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
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RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
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}
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static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
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{
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mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
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}
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static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
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{
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mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
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}
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static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
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{
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mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
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mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
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HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
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mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
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RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
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usleep_range(5, 10);
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mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
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HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
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mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
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mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
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RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
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}
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static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
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{
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void (*hpd_event)(bool hpd, struct device *dev);
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struct device *hdmi_dev;
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unsigned long flags;
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spin_lock_irqsave(&cec->lock, flags);
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hpd_event = cec->hpd_event;
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hdmi_dev = cec->hdmi_dev;
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spin_unlock_irqrestore(&cec->lock, flags);
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if (hpd_event)
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hpd_event(hpd, hdmi_dev);
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}
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static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
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{
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struct device *dev = arg;
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struct mtk_cec *cec = dev_get_drvdata(dev);
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bool hpd;
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mtk_cec_clear_htplg_irq(cec);
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hpd = mtk_cec_hpd_high(dev);
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if (cec->hpd != hpd) {
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dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
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cec->hpd, hpd);
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cec->hpd = hpd;
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mtk_cec_hpd_event(cec, hpd);
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}
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return IRQ_HANDLED;
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}
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static int mtk_cec_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_cec *cec;
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struct resource *res;
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int ret;
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cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
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if (!cec)
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return -ENOMEM;
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platform_set_drvdata(pdev, cec);
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spin_lock_init(&cec->lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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cec->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(cec->regs)) {
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ret = PTR_ERR(cec->regs);
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dev_err(dev, "Failed to ioremap cec: %d\n", ret);
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return ret;
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}
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cec->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(cec->clk)) {
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ret = PTR_ERR(cec->clk);
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dev_err(dev, "Failed to get cec clock: %d\n", ret);
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return ret;
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}
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cec->irq = platform_get_irq(pdev, 0);
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if (cec->irq < 0) {
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dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
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return cec->irq;
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}
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ret = devm_request_threaded_irq(dev, cec->irq, NULL,
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mtk_cec_htplg_isr_thread,
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IRQF_SHARED | IRQF_TRIGGER_LOW |
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IRQF_ONESHOT, "hdmi hpd", dev);
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if (ret) {
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dev_err(dev, "Failed to register cec irq: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(cec->clk);
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if (ret) {
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dev_err(dev, "Failed to enable cec clock: %d\n", ret);
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return ret;
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}
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mtk_cec_htplg_irq_init(cec);
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mtk_cec_htplg_irq_enable(cec);
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return 0;
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}
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static int mtk_cec_remove(struct platform_device *pdev)
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{
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struct mtk_cec *cec = platform_get_drvdata(pdev);
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mtk_cec_htplg_irq_disable(cec);
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clk_disable_unprepare(cec->clk);
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return 0;
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}
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static const struct of_device_id mtk_cec_of_ids[] = {
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{ .compatible = "mediatek,mt8173-cec", },
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{}
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};
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struct platform_driver mtk_cec_driver = {
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.probe = mtk_cec_probe,
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.remove = mtk_cec_remove,
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.driver = {
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.name = "mediatek-cec",
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.of_match_table = mtk_cec_of_ids,
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},
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};
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MTK_CEC_H
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#define _MTK_CEC_H
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#include <linux/types.h>
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struct device;
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void mtk_cec_set_hpd_event(struct device *dev,
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void (*hotplug_event)(bool hpd, struct device *dev),
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struct device *hdmi_dev);
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bool mtk_cec_hpd_high(struct device *dev);
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#endif /* _MTK_CEC_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MTK_HDMI_CTRL_H
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#define _MTK_HDMI_CTRL_H
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struct platform_driver;
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extern struct platform_driver mtk_cec_driver;
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extern struct platform_driver mtk_hdmi_ddc_driver;
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extern struct platform_driver mtk_hdmi_phy_driver;
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#endif /* _MTK_HDMI_CTRL_H */
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@ -0,0 +1,358 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#define SIF1_CLOK (288)
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#define DDC_DDCMCTL0 (0x0)
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#define DDCM_ODRAIN BIT(31)
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#define DDCM_CLK_DIV_OFFSET (16)
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#define DDCM_CLK_DIV_MASK (0xfff << 16)
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#define DDCM_CS_STATUS BIT(4)
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#define DDCM_SCL_STATE BIT(3)
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#define DDCM_SDA_STATE BIT(2)
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#define DDCM_SM0EN BIT(1)
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#define DDCM_SCL_STRECH BIT(0)
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#define DDC_DDCMCTL1 (0x4)
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#define DDCM_ACK_OFFSET (16)
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#define DDCM_ACK_MASK (0xff << 16)
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#define DDCM_PGLEN_OFFSET (8)
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#define DDCM_PGLEN_MASK (0x7 << 8)
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#define DDCM_SIF_MODE_OFFSET (4)
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#define DDCM_SIF_MODE_MASK (0x7 << 4)
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#define DDCM_START (0x1)
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#define DDCM_WRITE_DATA (0x2)
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#define DDCM_STOP (0x3)
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#define DDCM_READ_DATA_NO_ACK (0x4)
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#define DDCM_READ_DATA_ACK (0x5)
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#define DDCM_TRI BIT(0)
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#define DDC_DDCMD0 (0x8)
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#define DDCM_DATA3 (0xff << 24)
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#define DDCM_DATA2 (0xff << 16)
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#define DDCM_DATA1 (0xff << 8)
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#define DDCM_DATA0 (0xff << 0)
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#define DDC_DDCMD1 (0xc)
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#define DDCM_DATA7 (0xff << 24)
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#define DDCM_DATA6 (0xff << 16)
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#define DDCM_DATA5 (0xff << 8)
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#define DDCM_DATA4 (0xff << 0)
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struct mtk_hdmi_ddc {
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struct i2c_adapter adap;
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struct clk *clk;
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void __iomem *regs;
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};
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static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
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unsigned int val)
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{
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writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
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}
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static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
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unsigned int val)
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||||
{
|
||||
writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
|
||||
}
|
||||
|
||||
static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
|
||||
unsigned int val)
|
||||
{
|
||||
return (readl(ddc->regs + offset) & val) == val;
|
||||
}
|
||||
|
||||
static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
|
||||
unsigned int mask, unsigned int shift,
|
||||
unsigned int val)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = readl(ddc->regs + offset);
|
||||
tmp &= ~mask;
|
||||
tmp |= (val << shift) & mask;
|
||||
writel(tmp, ddc->regs + offset);
|
||||
}
|
||||
|
||||
static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
|
||||
unsigned int offset, unsigned int mask,
|
||||
unsigned int shift)
|
||||
{
|
||||
return (readl(ddc->regs + offset) & mask) >> shift;
|
||||
}
|
||||
|
||||
static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
|
||||
DDCM_SIF_MODE_OFFSET, mode);
|
||||
sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
|
||||
readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
|
||||
(val & DDCM_TRI) != DDCM_TRI, 4, 20000);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
|
||||
{
|
||||
struct device *dev = ddc->adap.dev.parent;
|
||||
u32 remain_count, ack_count, ack_final, read_count, temp_count;
|
||||
u32 index = 0;
|
||||
u32 ack;
|
||||
int i;
|
||||
|
||||
ddcm_trigger_mode(ddc, DDCM_START);
|
||||
sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
|
||||
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
|
||||
0x00);
|
||||
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
|
||||
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
|
||||
dev_dbg(dev, "ack = 0x%x\n", ack);
|
||||
if (ack != 0x01) {
|
||||
dev_err(dev, "i2c ack err!\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
remain_count = msg->len;
|
||||
ack_count = (msg->len - 1) / 8;
|
||||
ack_final = 0;
|
||||
|
||||
while (remain_count > 0) {
|
||||
if (ack_count > 0) {
|
||||
read_count = 8;
|
||||
ack_final = 0;
|
||||
ack_count--;
|
||||
} else {
|
||||
read_count = remain_count;
|
||||
ack_final = 1;
|
||||
}
|
||||
|
||||
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
|
||||
DDCM_PGLEN_OFFSET, read_count - 1);
|
||||
ddcm_trigger_mode(ddc, (ack_final == 1) ?
|
||||
DDCM_READ_DATA_NO_ACK :
|
||||
DDCM_READ_DATA_ACK);
|
||||
|
||||
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
|
||||
DDCM_ACK_OFFSET);
|
||||
temp_count = 0;
|
||||
while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
|
||||
temp_count++;
|
||||
if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
|
||||
((ack_final == 0) && (temp_count != read_count))) {
|
||||
dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = read_count; i >= 1; i--) {
|
||||
int shift;
|
||||
int offset;
|
||||
|
||||
if (i > 4) {
|
||||
offset = DDC_DDCMD1;
|
||||
shift = (i - 5) * 8;
|
||||
} else {
|
||||
offset = DDC_DDCMD0;
|
||||
shift = (i - 1) * 8;
|
||||
}
|
||||
|
||||
msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
|
||||
0xff << shift,
|
||||
shift);
|
||||
}
|
||||
|
||||
remain_count -= read_count;
|
||||
index += read_count;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
|
||||
{
|
||||
struct device *dev = ddc->adap.dev.parent;
|
||||
u32 ack;
|
||||
|
||||
ddcm_trigger_mode(ddc, DDCM_START);
|
||||
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
|
||||
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
|
||||
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
|
||||
0x1);
|
||||
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
|
||||
|
||||
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
|
||||
dev_dbg(dev, "ack = %d\n", ack);
|
||||
|
||||
if (ack != 0x03) {
|
||||
dev_err(dev, "i2c ack err!\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct mtk_hdmi_ddc *ddc = adapter->algo_data;
|
||||
struct device *dev = adapter->dev.parent;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
if (!ddc) {
|
||||
dev_err(dev, "invalid arguments\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
|
||||
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
|
||||
sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
|
||||
|
||||
if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
|
||||
dev_err(dev, "ddc line is busy!\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
|
||||
DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
struct i2c_msg *msg = &msgs[i];
|
||||
|
||||
dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
|
||||
msg->addr, msg->flags, msg->len);
|
||||
|
||||
if (msg->flags & I2C_M_RD)
|
||||
ret = mtk_hdmi_ddc_read_msg(ddc, msg);
|
||||
else
|
||||
ret = mtk_hdmi_ddc_write_msg(ddc, msg);
|
||||
if (ret < 0)
|
||||
goto xfer_end;
|
||||
}
|
||||
|
||||
ddcm_trigger_mode(ddc, DDCM_STOP);
|
||||
|
||||
return i;
|
||||
|
||||
xfer_end:
|
||||
ddcm_trigger_mode(ddc, DDCM_STOP);
|
||||
dev_err(dev, "ddc failed!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
|
||||
.master_xfer = mtk_hdmi_ddc_xfer,
|
||||
.functionality = mtk_hdmi_ddc_func,
|
||||
};
|
||||
|
||||
static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_hdmi_ddc *ddc;
|
||||
struct resource *mem;
|
||||
int ret;
|
||||
|
||||
ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
|
||||
if (!ddc)
|
||||
return -ENOMEM;
|
||||
|
||||
ddc->clk = devm_clk_get(dev, "ddc-i2c");
|
||||
if (IS_ERR(ddc->clk)) {
|
||||
dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
|
||||
return PTR_ERR(ddc->clk);
|
||||
}
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(ddc->regs))
|
||||
return PTR_ERR(ddc->regs);
|
||||
|
||||
ret = clk_prepare_enable(ddc->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "enable ddc clk failed!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
|
||||
ddc->adap.owner = THIS_MODULE;
|
||||
ddc->adap.class = I2C_CLASS_DDC;
|
||||
ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
|
||||
ddc->adap.retries = 3;
|
||||
ddc->adap.dev.of_node = dev->of_node;
|
||||
ddc->adap.algo_data = ddc;
|
||||
ddc->adap.dev.parent = &pdev->dev;
|
||||
|
||||
ret = i2c_add_adapter(&ddc->adap);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to add bus to i2c core\n");
|
||||
goto err_clk_disable;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, ddc);
|
||||
|
||||
dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
|
||||
dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
|
||||
dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
|
||||
&mem->end);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_disable:
|
||||
clk_disable_unprepare(ddc->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&ddc->adap);
|
||||
clk_disable_unprepare(ddc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hdmi_ddc_match[] = {
|
||||
{ .compatible = "mediatek,mt8173-hdmi-ddc", },
|
||||
{},
|
||||
};
|
||||
|
||||
struct platform_driver mtk_hdmi_ddc_driver = {
|
||||
.probe = mtk_hdmi_ddc_probe,
|
||||
.remove = mtk_hdmi_ddc_remove,
|
||||
.driver = {
|
||||
.name = "mediatek-hdmi-ddc",
|
||||
.of_match_table = mtk_hdmi_ddc_match,
|
||||
},
|
||||
};
|
||||
|
||||
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef _MTK_HDMI_REGS_H
|
||||
#define _MTK_HDMI_REGS_H
|
||||
|
||||
#define GRL_INT_MASK 0x18
|
||||
#define GRL_IFM_PORT 0x188
|
||||
#define GRL_CH_SWAP 0x198
|
||||
#define LR_SWAP BIT(0)
|
||||
#define LFE_CC_SWAP BIT(1)
|
||||
#define LSRS_SWAP BIT(2)
|
||||
#define RLS_RRS_SWAP BIT(3)
|
||||
#define LR_STATUS_SWAP BIT(4)
|
||||
#define GRL_I2S_C_STA0 0x140
|
||||
#define GRL_I2S_C_STA1 0x144
|
||||
#define GRL_I2S_C_STA2 0x148
|
||||
#define GRL_I2S_C_STA3 0x14C
|
||||
#define GRL_I2S_C_STA4 0x150
|
||||
#define GRL_I2S_UV 0x154
|
||||
#define I2S_UV_V BIT(0)
|
||||
#define I2S_UV_U BIT(1)
|
||||
#define I2S_UV_CH_EN_MASK 0x3c
|
||||
#define I2S_UV_CH_EN(x) BIT((x) + 2)
|
||||
#define I2S_UV_TMDS_DEBUG BIT(6)
|
||||
#define I2S_UV_NORMAL_INFO_INV BIT(7)
|
||||
#define GRL_ACP_ISRC_CTRL 0x158
|
||||
#define VS_EN BIT(0)
|
||||
#define ACP_EN BIT(1)
|
||||
#define ISRC1_EN BIT(2)
|
||||
#define ISRC2_EN BIT(3)
|
||||
#define GAMUT_EN BIT(4)
|
||||
#define GRL_CTS_CTRL 0x160
|
||||
#define CTS_CTRL_SOFT BIT(0)
|
||||
#define GRL_INT 0x14
|
||||
#define INT_MDI BIT(0)
|
||||
#define INT_HDCP BIT(1)
|
||||
#define INT_FIFO_O BIT(2)
|
||||
#define INT_FIFO_U BIT(3)
|
||||
#define INT_IFM_ERR BIT(4)
|
||||
#define INT_INF_DONE BIT(5)
|
||||
#define INT_NCTS_DONE BIT(6)
|
||||
#define INT_CTRL_PKT_DONE BIT(7)
|
||||
#define GRL_INT_MASK 0x18
|
||||
#define GRL_CTRL 0x1C
|
||||
#define CTRL_GEN_EN BIT(2)
|
||||
#define CTRL_SPD_EN BIT(3)
|
||||
#define CTRL_MPEG_EN BIT(4)
|
||||
#define CTRL_AUDIO_EN BIT(5)
|
||||
#define CTRL_AVI_EN BIT(6)
|
||||
#define CTRL_AVMUTE BIT(7)
|
||||
#define GRL_STATUS 0x20
|
||||
#define STATUS_HTPLG BIT(0)
|
||||
#define STATUS_PORD BIT(1)
|
||||
#define GRL_DIVN 0x170
|
||||
#define NCTS_WRI_ANYTIME BIT(6)
|
||||
#define GRL_AUDIO_CFG 0x17C
|
||||
#define AUDIO_ZERO BIT(0)
|
||||
#define HIGH_BIT_RATE BIT(1)
|
||||
#define SACD_DST BIT(2)
|
||||
#define DST_NORMAL_DOUBLE BIT(3)
|
||||
#define DSD_INV BIT(4)
|
||||
#define LR_INV BIT(5)
|
||||
#define LR_MIX BIT(6)
|
||||
#define DSD_SEL BIT(7)
|
||||
#define GRL_NCTS 0x184
|
||||
#define GRL_CH_SW0 0x18C
|
||||
#define GRL_CH_SW1 0x190
|
||||
#define GRL_CH_SW2 0x194
|
||||
#define CH_SWITCH(from, to) ((from) << ((to) * 3))
|
||||
#define GRL_INFOFRM_VER 0x19C
|
||||
#define GRL_INFOFRM_TYPE 0x1A0
|
||||
#define GRL_INFOFRM_LNG 0x1A4
|
||||
#define GRL_MIX_CTRL 0x1B4
|
||||
#define MIX_CTRL_SRC_EN BIT(0)
|
||||
#define BYPASS_VOLUME BIT(1)
|
||||
#define MIX_CTRL_FLAT BIT(7)
|
||||
#define GRL_AOUT_CFG 0x1C4
|
||||
#define AOUT_BNUM_SEL_MASK 0x03
|
||||
#define AOUT_24BIT 0x00
|
||||
#define AOUT_20BIT 0x02
|
||||
#define AOUT_16BIT 0x03
|
||||
#define AOUT_FIFO_ADAP_CTRL BIT(6)
|
||||
#define AOUT_BURST_PREAMBLE_EN BIT(7)
|
||||
#define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
|
||||
AOUT_FIFO_ADAP_CTRL)
|
||||
#define GRL_SHIFT_L1 0x1C0
|
||||
#define GRL_SHIFT_R2 0x1B0
|
||||
#define AUDIO_PACKET_OFF BIT(6)
|
||||
#define GRL_CFG0 0x24
|
||||
#define CFG0_I2S_MODE_MASK 0x3
|
||||
#define CFG0_I2S_MODE_RTJ 0x1
|
||||
#define CFG0_I2S_MODE_LTJ 0x0
|
||||
#define CFG0_I2S_MODE_I2S 0x2
|
||||
#define CFG0_W_LENGTH_MASK 0x30
|
||||
#define CFG0_W_LENGTH_24BIT 0x00
|
||||
#define CFG0_W_LENGTH_16BIT 0x10
|
||||
#define GRL_CFG1 0x28
|
||||
#define CFG1_EDG_SEL BIT(0)
|
||||
#define CFG1_SPDIF BIT(1)
|
||||
#define CFG1_DVI BIT(2)
|
||||
#define CFG1_HDCP_DEBUG BIT(3)
|
||||
#define GRL_CFG2 0x2c
|
||||
#define CFG2_MHL_DE_SEL BIT(3)
|
||||
#define CFG2_MHL_FAKE_DE_SEL BIT(4)
|
||||
#define CFG2_MHL_DATA_REMAP BIT(5)
|
||||
#define CFG2_NOTICE_EN BIT(6)
|
||||
#define CFG2_ACLK_INV BIT(7)
|
||||
#define GRL_CFG3 0x30
|
||||
#define CFG3_AES_KEY_INDEX_MASK 0x3f
|
||||
#define CFG3_CONTROL_PACKET_DELAY BIT(6)
|
||||
#define CFG3_KSV_LOAD_START BIT(7)
|
||||
#define GRL_CFG4 0x34
|
||||
#define CFG4_AES_KEY_LOAD BIT(4)
|
||||
#define CFG4_AV_UNMUTE_EN BIT(5)
|
||||
#define CFG4_AV_UNMUTE_SET BIT(6)
|
||||
#define CFG4_MHL_MODE BIT(7)
|
||||
#define GRL_CFG5 0x38
|
||||
#define CFG5_CD_RATIO_MASK 0x8F
|
||||
#define CFG5_FS128 (0x1 << 4)
|
||||
#define CFG5_FS256 (0x2 << 4)
|
||||
#define CFG5_FS384 (0x3 << 4)
|
||||
#define CFG5_FS512 (0x4 << 4)
|
||||
#define CFG5_FS768 (0x6 << 4)
|
||||
#define DUMMY_304 0x304
|
||||
#define CHMO_SEL (0x3 << 2)
|
||||
#define CHM1_SEL (0x3 << 4)
|
||||
#define CHM2_SEL (0x3 << 6)
|
||||
#define AUDIO_I2S_NCTS_SEL BIT(1)
|
||||
#define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
|
||||
#define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
|
||||
#define NEW_GCP_CTRL BIT(0)
|
||||
#define NEW_GCP_CTRL_MERGE BIT(0)
|
||||
#define GRL_L_STATUS_0 0x200
|
||||
#define GRL_L_STATUS_1 0x204
|
||||
#define GRL_L_STATUS_2 0x208
|
||||
#define GRL_L_STATUS_3 0x20c
|
||||
#define GRL_L_STATUS_4 0x210
|
||||
#define GRL_L_STATUS_5 0x214
|
||||
#define GRL_L_STATUS_6 0x218
|
||||
#define GRL_L_STATUS_7 0x21c
|
||||
#define GRL_L_STATUS_8 0x220
|
||||
#define GRL_L_STATUS_9 0x224
|
||||
#define GRL_L_STATUS_10 0x228
|
||||
#define GRL_L_STATUS_11 0x22c
|
||||
#define GRL_L_STATUS_12 0x230
|
||||
#define GRL_L_STATUS_13 0x234
|
||||
#define GRL_L_STATUS_14 0x238
|
||||
#define GRL_L_STATUS_15 0x23c
|
||||
#define GRL_L_STATUS_16 0x240
|
||||
#define GRL_L_STATUS_17 0x244
|
||||
#define GRL_L_STATUS_18 0x248
|
||||
#define GRL_L_STATUS_19 0x24c
|
||||
#define GRL_L_STATUS_20 0x250
|
||||
#define GRL_L_STATUS_21 0x254
|
||||
#define GRL_L_STATUS_22 0x258
|
||||
#define GRL_L_STATUS_23 0x25c
|
||||
#define GRL_R_STATUS_0 0x260
|
||||
#define GRL_R_STATUS_1 0x264
|
||||
#define GRL_R_STATUS_2 0x268
|
||||
#define GRL_R_STATUS_3 0x26c
|
||||
#define GRL_R_STATUS_4 0x270
|
||||
#define GRL_R_STATUS_5 0x274
|
||||
#define GRL_R_STATUS_6 0x278
|
||||
#define GRL_R_STATUS_7 0x27c
|
||||
#define GRL_R_STATUS_8 0x280
|
||||
#define GRL_R_STATUS_9 0x284
|
||||
#define GRL_R_STATUS_10 0x288
|
||||
#define GRL_R_STATUS_11 0x28c
|
||||
#define GRL_R_STATUS_12 0x290
|
||||
#define GRL_R_STATUS_13 0x294
|
||||
#define GRL_R_STATUS_14 0x298
|
||||
#define GRL_R_STATUS_15 0x29c
|
||||
#define GRL_R_STATUS_16 0x2a0
|
||||
#define GRL_R_STATUS_17 0x2a4
|
||||
#define GRL_R_STATUS_18 0x2a8
|
||||
#define GRL_R_STATUS_19 0x2ac
|
||||
#define GRL_R_STATUS_20 0x2b0
|
||||
#define GRL_R_STATUS_21 0x2b4
|
||||
#define GRL_R_STATUS_22 0x2b8
|
||||
#define GRL_R_STATUS_23 0x2bc
|
||||
#define GRL_ABIST_CTRL0 0x2D4
|
||||
#define GRL_ABIST_CTRL1 0x2D8
|
||||
#define ABIST_EN BIT(7)
|
||||
#define ABIST_DATA_FMT (0x7 << 0)
|
||||
#define VIDEO_CFG_0 0x380
|
||||
#define VIDEO_CFG_1 0x384
|
||||
#define VIDEO_CFG_2 0x388
|
||||
#define VIDEO_CFG_3 0x38c
|
||||
#define VIDEO_CFG_4 0x390
|
||||
#define VIDEO_SOURCE_SEL BIT(7)
|
||||
#define NORMAL_PATH (1 << 7)
|
||||
#define GEN_RGB (0 << 7)
|
||||
|
||||
#define HDMI_SYS_CFG1C 0x000
|
||||
#define HDMI_ON BIT(0)
|
||||
#define HDMI_RST BIT(1)
|
||||
#define ANLG_ON BIT(2)
|
||||
#define CFG10_DVI BIT(3)
|
||||
#define HDMI_TST BIT(3)
|
||||
#define SYS_KEYMASK1 (0xff << 8)
|
||||
#define SYS_KEYMASK2 (0xff << 16)
|
||||
#define AUD_OUTSYNC_EN BIT(24)
|
||||
#define AUD_OUTSYNC_PRE_EN BIT(25)
|
||||
#define I2CM_ON BIT(26)
|
||||
#define E2PROM_TYPE_8BIT BIT(27)
|
||||
#define MCM_E2PROM_ON BIT(28)
|
||||
#define EXT_E2PROM_ON BIT(29)
|
||||
#define HTPLG_PIN_SEL_OFF BIT(30)
|
||||
#define AES_EFUSE_ENABLE BIT(31)
|
||||
#define HDMI_SYS_CFG20 0x004
|
||||
#define DEEP_COLOR_MODE_MASK (3 << 1)
|
||||
#define COLOR_8BIT_MODE (0 << 1)
|
||||
#define COLOR_10BIT_MODE (1 << 1)
|
||||
#define COLOR_12BIT_MODE (2 << 1)
|
||||
#define COLOR_16BIT_MODE (3 << 1)
|
||||
#define DEEP_COLOR_EN BIT(0)
|
||||
#define HDMI_AUDIO_TEST_SEL BIT(8)
|
||||
#define HDMI2P0_EN BIT(11)
|
||||
#define HDMI_OUT_FIFO_EN BIT(16)
|
||||
#define HDMI_OUT_FIFO_CLK_INV BIT(17)
|
||||
#define MHL_MODE_ON BIT(28)
|
||||
#define MHL_PP_MODE BIT(29)
|
||||
#define MHL_SYNC_AUTO_EN BIT(30)
|
||||
#define HDMI_PCLK_FREE_RUN BIT(31)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,515 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define HDMI_CON0 0x00
|
||||
#define RG_HDMITX_PLL_EN BIT(31)
|
||||
#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
|
||||
#define PLL_FBKDIV_SHIFT 24
|
||||
#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
|
||||
#define PLL_FBKSEL_SHIFT 22
|
||||
#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
|
||||
#define PREDIV_SHIFT 20
|
||||
#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
|
||||
#define POSDIV_SHIFT 18
|
||||
#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
|
||||
#define RG_HDMITX_PLL_IR (0xf << 12)
|
||||
#define PLL_IR_SHIFT 12
|
||||
#define RG_HDMITX_PLL_IC (0xf << 8)
|
||||
#define PLL_IC_SHIFT 8
|
||||
#define RG_HDMITX_PLL_BP (0xf << 4)
|
||||
#define PLL_BP_SHIFT 4
|
||||
#define RG_HDMITX_PLL_BR (0x3 << 2)
|
||||
#define PLL_BR_SHIFT 2
|
||||
#define RG_HDMITX_PLL_BC (0x3 << 0)
|
||||
#define PLL_BC_SHIFT 0
|
||||
#define HDMI_CON1 0x04
|
||||
#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
|
||||
#define PLL_DIVEN_SHIFT 29
|
||||
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
|
||||
#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
|
||||
#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
|
||||
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
|
||||
#define RG_HDMITX_PLL_BAND (0x3f << 16)
|
||||
#define RG_HDMITX_PLL_REF_SEL BIT(15)
|
||||
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
|
||||
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
|
||||
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
|
||||
#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
|
||||
#define PLL_TXDIV_SHIFT 10
|
||||
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
|
||||
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
|
||||
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
|
||||
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
|
||||
#define RG_HDMITX_PLL_TST_EN BIT(5)
|
||||
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
|
||||
#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
|
||||
#define HDMI_CON2 0x08
|
||||
#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
|
||||
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
|
||||
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
|
||||
#define HDMI_CON3 0x0c
|
||||
#define RG_HDMITX_SER_EN (0xf << 28)
|
||||
#define RG_HDMITX_PRD_EN (0xf << 24)
|
||||
#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
|
||||
#define RG_HDMITX_DRV_EN (0xf << 16)
|
||||
#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
|
||||
#define DRV_IMP_EN_SHIFT 12
|
||||
#define RG_HDMITX_MHLCK_FORCE BIT(10)
|
||||
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
|
||||
#define RG_HDMITX_MHLCK_EN BIT(8)
|
||||
#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
|
||||
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
|
||||
#define RG_HDMITX_SER_BIST_TOG BIT(2)
|
||||
#define RG_HDMITX_SER_DIN_TOG BIT(1)
|
||||
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
|
||||
#define HDMI_CON4 0x10
|
||||
#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
|
||||
#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
|
||||
#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
|
||||
#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
|
||||
#define PRD_IBIAS_CLK_SHIFT 24
|
||||
#define PRD_IBIAS_D2_SHIFT 16
|
||||
#define PRD_IBIAS_D1_SHIFT 8
|
||||
#define PRD_IBIAS_D0_SHIFT 0
|
||||
#define HDMI_CON5 0x14
|
||||
#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
|
||||
#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
|
||||
#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
|
||||
#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
|
||||
#define DRV_IBIAS_CLK_SHIFT 24
|
||||
#define DRV_IBIAS_D2_SHIFT 16
|
||||
#define DRV_IBIAS_D1_SHIFT 8
|
||||
#define DRV_IBIAS_D0_SHIFT 0
|
||||
#define HDMI_CON6 0x18
|
||||
#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
|
||||
#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
|
||||
#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
|
||||
#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
|
||||
#define DRV_IMP_CLK_SHIFT 24
|
||||
#define DRV_IMP_D2_SHIFT 16
|
||||
#define DRV_IMP_D1_SHIFT 8
|
||||
#define DRV_IMP_D0_SHIFT 0
|
||||
#define HDMI_CON7 0x1c
|
||||
#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
|
||||
#define RG_HDMITX_SER_DIN (0x3ff << 16)
|
||||
#define RG_HDMITX_CHLDC_TST (0xf << 12)
|
||||
#define RG_HDMITX_CHLCK_TST (0xf << 8)
|
||||
#define RG_HDMITX_RESERVE (0xff << 0)
|
||||
#define HDMI_CON8 0x20
|
||||
#define RGS_HDMITX_2T1_LEV (0xf << 16)
|
||||
#define RGS_HDMITX_2T1_EDG (0xf << 12)
|
||||
#define RGS_HDMITX_5T1_LEV (0xf << 8)
|
||||
#define RGS_HDMITX_5T1_EDG (0xf << 4)
|
||||
#define RGS_HDMITX_PLUG_TST BIT(0)
|
||||
|
||||
struct mtk_hdmi_phy {
|
||||
void __iomem *regs;
|
||||
struct device *dev;
|
||||
struct clk *pll;
|
||||
struct clk_hw pll_hw;
|
||||
unsigned long pll_rate;
|
||||
u8 drv_imp_clk;
|
||||
u8 drv_imp_d2;
|
||||
u8 drv_imp_d1;
|
||||
u8 drv_imp_d0;
|
||||
u32 ibias;
|
||||
u32 ibias_up;
|
||||
};
|
||||
|
||||
static const u8 PREDIV[3][4] = {
|
||||
{0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
|
||||
{0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
|
||||
{0x1, 0x1, 0x1, 0x1} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 TXDIV[3][4] = {
|
||||
{0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
|
||||
{0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
|
||||
{0x1, 0x0, 0x0, 0x0} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 FBKSEL[3][4] = {
|
||||
{0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
|
||||
{0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
|
||||
{0x1, 0x0, 0x1, 0x1} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 FBKDIV[3][4] = {
|
||||
{19, 24, 29, 19}, /* 27Mhz */
|
||||
{19, 24, 14, 19}, /* 74Mhz */
|
||||
{19, 24, 14, 19} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 DIVEN[3][4] = {
|
||||
{0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
|
||||
{0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
|
||||
{0x2, 0x2, 0x2, 0x2} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 HTPLLBP[3][4] = {
|
||||
{0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
|
||||
{0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
|
||||
{0xc, 0xf, 0xf, 0xc} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 HTPLLBC[3][4] = {
|
||||
{0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
|
||||
{0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
|
||||
{0x2, 0x3, 0x3, 0x2} /* 148Mhz */
|
||||
};
|
||||
|
||||
static const u8 HTPLLBR[3][4] = {
|
||||
{0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
|
||||
{0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
|
||||
{0x1, 0x2, 0x2, 0x1} /* 148Mhz */
|
||||
};
|
||||
|
||||
static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp &= ~bits;
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp |= bits;
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp = (tmp & ~mask) | (val & mask);
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
static inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_hdmi_phy, pll_hw);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
|
||||
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
|
||||
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
unsigned int pre_div;
|
||||
unsigned int div;
|
||||
|
||||
dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
|
||||
rate, parent_rate);
|
||||
|
||||
if (rate <= 27000000) {
|
||||
pre_div = 0;
|
||||
div = 3;
|
||||
} else if (rate <= 74250000) {
|
||||
pre_div = 1;
|
||||
div = 2;
|
||||
} else {
|
||||
pre_div = 1;
|
||||
div = 1;
|
||||
}
|
||||
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
|
||||
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
|
||||
(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
|
||||
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
|
||||
(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
|
||||
(0x1 << PLL_BR_SHIFT),
|
||||
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
|
||||
RG_HDMITX_PLL_BR);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
|
||||
(0x3 << PRD_IBIAS_CLK_SHIFT) |
|
||||
(0x3 << PRD_IBIAS_D2_SHIFT) |
|
||||
(0x3 << PRD_IBIAS_D1_SHIFT) |
|
||||
(0x3 << PRD_IBIAS_D0_SHIFT),
|
||||
RG_HDMITX_PRD_IBIAS_CLK |
|
||||
RG_HDMITX_PRD_IBIAS_D2 |
|
||||
RG_HDMITX_PRD_IBIAS_D1 |
|
||||
RG_HDMITX_PRD_IBIAS_D0);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
|
||||
(0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
|
||||
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
|
||||
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
|
||||
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
|
||||
(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
|
||||
(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
|
||||
(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
|
||||
(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
|
||||
RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
|
||||
RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
hdmi_phy->pll_rate = rate;
|
||||
if (rate <= 74250000)
|
||||
*parent_rate = rate;
|
||||
else
|
||||
*parent_rate = rate / 2;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
return hdmi_phy->pll_rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_hdmi_pll_ops = {
|
||||
.prepare = mtk_hdmi_pll_prepare,
|
||||
.unprepare = mtk_hdmi_pll_unprepare,
|
||||
.set_rate = mtk_hdmi_pll_set_rate,
|
||||
.round_rate = mtk_hdmi_pll_round_rate,
|
||||
.recalc_rate = mtk_hdmi_pll_recalc_rate,
|
||||
};
|
||||
|
||||
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
|
||||
RG_HDMITX_DRV_EN);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
|
||||
RG_HDMITX_SER_EN);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(hdmi_phy->pll);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
mtk_hdmi_phy_enable_tmds(hdmi_phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
|
||||
mtk_hdmi_phy_disable_tmds(hdmi_phy);
|
||||
clk_disable_unprepare(hdmi_phy->pll);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops mtk_hdmi_phy_ops = {
|
||||
.power_on = mtk_hdmi_phy_power_on,
|
||||
.power_off = mtk_hdmi_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int mtk_hdmi_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_hdmi_phy *hdmi_phy;
|
||||
struct resource *mem;
|
||||
struct clk *ref_clk;
|
||||
const char *ref_clk_name;
|
||||
struct clk_init_data clk_init = {
|
||||
.ops = &mtk_hdmi_pll_ops,
|
||||
.num_parents = 1,
|
||||
.parent_names = (const char * const *)&ref_clk_name,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
|
||||
};
|
||||
struct phy *phy;
|
||||
struct phy_provider *phy_provider;
|
||||
int ret;
|
||||
|
||||
hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
|
||||
if (!hdmi_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hdmi_phy->regs = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(hdmi_phy->regs)) {
|
||||
ret = PTR_ERR(hdmi_phy->regs);
|
||||
dev_err(dev, "Failed to get memory resource: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ref_clk = devm_clk_get(dev, "pll_ref");
|
||||
if (IS_ERR(ref_clk)) {
|
||||
ret = PTR_ERR(ref_clk);
|
||||
dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
ref_clk_name = __clk_get_name(ref_clk);
|
||||
|
||||
ret = of_property_read_string(dev->of_node, "clock-output-names",
|
||||
&clk_init.name);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
hdmi_phy->pll_hw.init = &clk_init;
|
||||
hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
|
||||
if (IS_ERR(hdmi_phy->pll)) {
|
||||
ret = PTR_ERR(hdmi_phy->pll);
|
||||
dev_err(dev, "Failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
|
||||
&hdmi_phy->ibias);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
|
||||
&hdmi_phy->ibias_up);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
|
||||
hdmi_phy->drv_imp_clk = 0x30;
|
||||
hdmi_phy->drv_imp_d2 = 0x30;
|
||||
hdmi_phy->drv_imp_d1 = 0x30;
|
||||
hdmi_phy->drv_imp_d0 = 0x30;
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "Failed to create HDMI PHY\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
phy_set_drvdata(phy, hdmi_phy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider))
|
||||
return PTR_ERR(phy_provider);
|
||||
|
||||
hdmi_phy->dev = dev;
|
||||
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
|
||||
hdmi_phy->pll);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hdmi_phy_match[] = {
|
||||
{ .compatible = "mediatek,mt8173-hdmi-phy", },
|
||||
{},
|
||||
};
|
||||
|
||||
struct platform_driver mtk_hdmi_phy_driver = {
|
||||
.probe = mtk_hdmi_phy_probe,
|
||||
.remove = mtk_hdmi_phy_remove,
|
||||
.driver = {
|
||||
.name = "mediatek-hdmi-phy",
|
||||
.of_match_table = mtk_hdmi_phy_match,
|
||||
},
|
||||
};
|
||||
|
||||
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue