nios2: fix cache coherency
There is intermittent cache coherency issue caught in toolchian tests. Revert to use flushd. Signed-off-by: Ley Foon Tan <lftan@altera.com>
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@ -23,22 +23,6 @@ static void __flush_dcache(unsigned long start, unsigned long end)
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end += (cpuinfo.dcache_line_size - 1);
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end &= ~(cpuinfo.dcache_line_size - 1);
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for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
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__asm__ __volatile__ (" flushda 0(%0)\n"
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: /* Outputs */
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: /* Inputs */ "r"(addr)
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/* : No clobber */);
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}
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}
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static void __flush_dcache_all(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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start &= ~(cpuinfo.dcache_line_size - 1);
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end += (cpuinfo.dcache_line_size - 1);
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end &= ~(cpuinfo.dcache_line_size - 1);
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if (end > start + cpuinfo.dcache_size)
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end = start + cpuinfo.dcache_size;
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@ -112,7 +96,7 @@ static void flush_aliases(struct address_space *mapping, struct page *page)
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void flush_cache_all(void)
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{
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__flush_dcache_all(0, cpuinfo.dcache_size);
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__flush_dcache(0, cpuinfo.dcache_size);
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__flush_icache(0, cpuinfo.icache_size);
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}
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@ -182,7 +166,7 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
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*/
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unsigned long start = (unsigned long)page_address(page);
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__flush_dcache_all(start, start + PAGE_SIZE);
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__flush_dcache(start, start + PAGE_SIZE);
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}
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void flush_dcache_page(struct page *page)
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@ -268,7 +252,7 @@ void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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{
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flush_cache_page(vma, user_vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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__flush_dcache_all((unsigned long)src, (unsigned long)src + len);
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__flush_dcache((unsigned long)src, (unsigned long)src + len);
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if (vma->vm_flags & VM_EXEC)
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__flush_icache((unsigned long)src, (unsigned long)src + len);
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}
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@ -279,7 +263,7 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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{
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flush_cache_page(vma, user_vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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__flush_dcache_all((unsigned long)dst, (unsigned long)dst + len);
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__flush_dcache((unsigned long)dst, (unsigned long)dst + len);
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if (vma->vm_flags & VM_EXEC)
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__flush_icache((unsigned long)dst, (unsigned long)dst + len);
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}
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