PCI: tegra: Fix argument order in tegra_pcie_phy_disable()
The tegra_pcie_phy_disable() path called pads_writel() with arguments in
the wrong order. Swap them to be the "value, offset" order expected by
pads_writel().
Fixes: 6fe7c187e0
("PCI: tegra: Support per-lane PHYs")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
CC: stable@vger.kernel.org # v4.7+
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@ -859,7 +859,7 @@ static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
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/* override IDDQ */
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value = pads_readl(pcie, PADS_CTL);
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value |= PADS_CTL_IDDQ_1L;
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pads_writel(pcie, PADS_CTL, value);
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pads_writel(pcie, value, PADS_CTL);
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/* reset PLL */
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value = pads_readl(pcie, soc->pads_pll_ctl);
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