PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver
Add driver for the Socionext UniPhier Pro5 SoC endpoint controller. This controller is based on the DesignWare PCIe core. And add "host" to existing controller descriontions for the host controller in Kconfig. Link: https://lore.kernel.org/r/1589457801-12796-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Kunihiko Hayashi
Lorenzo Pieralisi
parent
eeab133e1f
commit
8d7e33d681
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@ -13143,7 +13143,7 @@ M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/uniphier-pcie*
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F: drivers/pci/controller/dwc/pcie-uniphier.c
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F: drivers/pci/controller/dwc/pcie-uniphier*
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PCIE DRIVER FOR ST SPEAR13XX
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M: Pratyush Anand <pratyush.anand@gmail.com>
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@ -281,15 +281,25 @@ config PCIE_TEGRA194_EP
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selected. This uses the DesignWare core.
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config PCIE_UNIPHIER
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bool "Socionext UniPhier PCIe controllers"
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bool "Socionext UniPhier PCIe host controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on UniPhier SoCs.
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Say Y here if you want PCIe host controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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config PCIE_UNIPHIER_EP
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bool "Socionext UniPhier PCIe endpoint controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here if you want PCIe endpoint controller support on
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UniPhier SoCs. This driver supports Pro5 SoC.
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config PCIE_AL
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bool "Amazon Annapurna Labs PCIe controller"
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depends on OF && (ARM64 || COMPILE_TEST)
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@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
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obj-$(CONFIG_PCI_MESON) += pci-meson.o
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obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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@ -0,0 +1,383 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe endpoint controller driver for UniPhier SoCs
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* Copyright 2018 Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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/* Link Glue registers */
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#define PCL_RSTCTRL0 0x0010
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#define PCL_RSTCTRL_AXI_REG BIT(3)
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#define PCL_RSTCTRL_AXI_SLAVE BIT(2)
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#define PCL_RSTCTRL_AXI_MASTER BIT(1)
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#define PCL_RSTCTRL_PIPE3 BIT(0)
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#define PCL_RSTCTRL1 0x0020
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#define PCL_RSTCTRL_PERST BIT(0)
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#define PCL_RSTCTRL2 0x0024
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#define PCL_RSTCTRL_PHY_RESET BIT(0)
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#define PCL_MODE 0x8000
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#define PCL_MODE_REGEN BIT(8)
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#define PCL_MODE_REGVAL BIT(0)
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#define PCL_APP_CLK_CTRL 0x8004
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#define PCL_APP_CLK_REQ BIT(0)
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#define PCL_APP_READY_CTRL 0x8008
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#define PCL_APP_LTSSM_ENABLE BIT(0)
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#define PCL_APP_MSI0 0x8040
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#define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8)
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#define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0)
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#define PCL_APP_MSI1 0x8044
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#define PCL_APP_MSI_REQ BIT(0)
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#define PCL_APP_INTX 0x8074
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#define PCL_APP_INTX_SYS_INT BIT(0)
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/* assertion time of INTx in usec */
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#define PCL_INTX_WIDTH_USEC 30
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struct uniphier_pcie_ep_priv {
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void __iomem *base;
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struct dw_pcie pci;
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struct clk *clk, *clk_gio;
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struct reset_control *rst, *rst_gio;
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struct phy *phy;
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const struct pci_epc_features *features;
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};
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#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
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static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv,
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bool enable)
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{
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u32 val;
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val = readl(priv->base + PCL_APP_READY_CTRL);
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if (enable)
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val |= PCL_APP_LTSSM_ENABLE;
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else
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val &= ~PCL_APP_LTSSM_ENABLE;
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writel(val, priv->base + PCL_APP_READY_CTRL);
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}
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static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
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bool assert)
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{
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u32 val;
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val = readl(priv->base + PCL_RSTCTRL2);
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if (assert)
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val |= PCL_RSTCTRL_PHY_RESET;
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else
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val &= ~PCL_RSTCTRL_PHY_RESET;
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writel(val, priv->base + PCL_RSTCTRL2);
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}
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static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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/* set EP mode */
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val = readl(priv->base + PCL_MODE);
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val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
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writel(val, priv->base + PCL_MODE);
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/* clock request */
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val = readl(priv->base + PCL_APP_CLK_CTRL);
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val &= ~PCL_APP_CLK_REQ;
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writel(val, priv->base + PCL_APP_CLK_CTRL);
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/* deassert PIPE3 and AXI reset */
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val = readl(priv->base + PCL_RSTCTRL0);
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val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
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| PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3;
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writel(val, priv->base + PCL_RSTCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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msleep(100);
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}
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static int uniphier_pcie_start_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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uniphier_pcie_ltssm_enable(priv, true);
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return 0;
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}
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static void uniphier_pcie_stop_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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uniphier_pcie_ltssm_enable(priv, false);
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}
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static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum pci_barno bar;
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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}
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static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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/*
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* This makes pulse signal to send INTx to the RC, so this should
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* be cleared as soon as possible. This sequence is covered with
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* mutex in pci_epc_raise_irq().
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*/
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/* assert INTx */
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val = readl(priv->base + PCL_APP_INTX);
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val |= PCL_APP_INTX_SYS_INT;
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writel(val, priv->base + PCL_APP_INTX);
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udelay(PCL_INTX_WIDTH_USEC);
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/* deassert INTx */
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val &= ~PCL_APP_INTX_SYS_INT;
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writel(val, priv->base + PCL_APP_INTX);
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return 0;
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}
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static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
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u8 func_no, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no)
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| FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1);
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writel(val, priv->base + PCL_APP_MSI0);
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val = readl(priv->base + PCL_APP_MSI1);
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val |= PCL_APP_MSI_REQ;
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writel(val, priv->base + PCL_APP_MSI1);
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return 0;
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}
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static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type,
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u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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return uniphier_pcie_ep_raise_legacy_irq(ep);
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case PCI_EPC_IRQ_MSI:
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return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
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interrupt_num);
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type);
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}
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return 0;
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}
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static const struct pci_epc_features*
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uniphier_pcie_get_features(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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return priv->features;
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}
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static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
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.ep_init = uniphier_pcie_ep_init,
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.raise_irq = uniphier_pcie_ep_raise_irq,
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.get_features = uniphier_pcie_get_features,
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};
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static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = &priv->pci;
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struct dw_pcie_ep *ep = &pci->ep;
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struct device *dev = &pdev->dev;
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struct resource *res;
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int ret;
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ep->ops = &uniphier_pcie_ep_ops;
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pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
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if (IS_ERR(pci->dbi_base2))
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return PTR_ERR(pci->dbi_base2);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret)
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dev_err(dev, "Failed to initialize endpoint (%d)\n", ret);
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return ret;
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}
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static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
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{
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clk_gio);
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if (ret)
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goto out_clk_disable;
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ret = reset_control_deassert(priv->rst);
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if (ret)
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goto out_clk_gio_disable;
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ret = reset_control_deassert(priv->rst_gio);
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if (ret)
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goto out_rst_assert;
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uniphier_pcie_init_ep(priv);
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uniphier_pcie_phy_reset(priv, true);
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ret = phy_init(priv->phy);
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if (ret)
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goto out_rst_gio_assert;
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uniphier_pcie_phy_reset(priv, false);
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return 0;
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out_rst_gio_assert:
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reset_control_assert(priv->rst_gio);
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out_rst_assert:
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reset_control_assert(priv->rst);
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out_clk_gio_disable:
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clk_disable_unprepare(priv->clk_gio);
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out_clk_disable:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.start_link = uniphier_pcie_start_link,
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.stop_link = uniphier_pcie_stop_link,
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};
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static int uniphier_pcie_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_pcie_ep_priv *priv;
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struct resource *res;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->features = of_device_get_match_data(dev);
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if (WARN_ON(!priv->features))
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return -EINVAL;
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priv->pci.dev = dev;
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priv->pci.ops = &dw_pcie_ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(priv->pci.dbi_base))
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return PTR_ERR(priv->pci.dbi_base);
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priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk_gio = devm_clk_get(dev, "gio");
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if (IS_ERR(priv->clk_gio))
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return PTR_ERR(priv->clk_gio);
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priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
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if (IS_ERR(priv->rst_gio))
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return PTR_ERR(priv->rst_gio);
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priv->clk = devm_clk_get(dev, "link");
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->rst = devm_reset_control_get_shared(dev, "link");
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if (IS_ERR(priv->rst))
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return PTR_ERR(priv->rst);
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priv->phy = devm_phy_optional_get(dev, "pcie-phy");
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if (IS_ERR(priv->phy)) {
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ret = PTR_ERR(priv->phy);
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dev_err(dev, "Failed to get phy (%d)\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, priv);
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ret = uniphier_pcie_ep_enable(priv);
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if (ret)
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return ret;
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return uniphier_add_pcie_ep(priv, pdev);
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}
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static const struct pci_epc_features uniphier_pro5_data = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.align = 1 << 16,
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
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.reserved_bar = BIT(BAR_4),
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};
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static const struct of_device_id uniphier_pcie_ep_match[] = {
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{
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.compatible = "socionext,uniphier-pro5-pcie-ep",
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.data = &uniphier_pro5_data,
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},
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{ /* sentinel */ },
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};
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static struct platform_driver uniphier_pcie_ep_driver = {
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.probe = uniphier_pcie_ep_probe,
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.driver = {
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.name = "uniphier-pcie-ep",
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.of_match_table = uniphier_pcie_ep_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(uniphier_pcie_ep_driver);
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