Merge branch 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

From Shawn Guo <shawn.guo@linaro.org>:

Here is the second (last) batch of imx device tree changes for 3.6.

* 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: imx6q: ensure ANATOP controller is available
  ARM: dts: imx6q-sabrelite: add ecspi1 pinctrl support
  ARM: dts: imx6q-sabrelite: add usb devices
  ARM: imx6q: disable usb charger detector
  ARM: imx6q: add usbphy clocks
  ARM: imx6q: add usb controller clock lookups
  ARM: dts: imx: update #interrupt-cells for gpio nodes
  bindings: update imx and mxs #gpio-cells

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-07-12 14:49:00 +02:00
commit 8d5776d5fe
10 changed files with 166 additions and 31 deletions

View File

@ -8,8 +8,16 @@ Required properties:
by low 16 pins and the second one is for high 16 pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2. The first cell is the GPIO number.
The second cell bits[3:0] is used to specify trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Example:
@ -19,4 +27,6 @@ gpio0: gpio@73f84000 {
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

View File

@ -13,8 +13,9 @@ Required properties for GPIO node:
- interrupts : Should be the port interrupt shared by all 32 pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2. The first cell is the GPIO number.
The second cell bits[3:0] is used to specify trigger type and level flags:

View File

@ -121,7 +121,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@10015100 {
@ -131,7 +131,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@10015200 {
@ -141,7 +141,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@10015300 {
@ -151,7 +151,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@10015400 {
@ -161,7 +161,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@10015500 {
@ -171,7 +171,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
cspi3: cspi@10017000 {

View File

@ -133,7 +133,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@73f88000 {
@ -143,7 +143,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@73f8c000 {
@ -153,7 +153,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@73f90000 {
@ -163,7 +163,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
wdog@73f98000 { /* WDOG1 */

View File

@ -135,7 +135,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@53f88000 {
@ -145,7 +145,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@53f8c000 {
@ -155,7 +155,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@53f90000 {
@ -165,7 +165,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
wdog@53f98000 { /* WDOG1 */
@ -203,7 +203,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@53fe0000 {
@ -213,7 +213,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio7: gpio@53fe4000 {
@ -223,7 +223,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
i2c@53fec000 { /* I2C3 */

View File

@ -27,6 +27,8 @@
ecspi@02008000 { /* eCSPI1 */
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
status = "okay";
flash: m25p80@0 {
@ -42,9 +44,31 @@
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_hog>;
gpios {
pinctrl_gpio_hog: gpiohog {
fsl,pins = <
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
usb@02184000 { /* USB OTG */
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
usb@02184200 { /* USB1 */
status = "okay";
};
ethernet@02188000 {
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
@ -111,6 +135,15 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: usb_otg_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
sound {

View File

@ -283,7 +283,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@020a0000 {
@ -293,7 +293,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@020a4000 {
@ -303,7 +303,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@020a8000 {
@ -313,7 +313,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@020ac000 {
@ -323,7 +323,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@020b0000 {
@ -333,7 +333,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio7: gpio@020b4000 {
@ -343,7 +343,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
kpp@020b8000 {
@ -461,12 +461,14 @@
};
};
usbphy@020c9000 { /* USBPHY1 */
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
};
usbphy@020ca000 { /* USBPHY2 */
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
};
@ -579,6 +581,14 @@
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
};
};
};
dcic@020e4000 { /* DCIC1 */
@ -614,6 +624,36 @@
reg = <0x0217c000 0x4000>;
};
usb@02184000 { /* USB OTG */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
};
usb@02184200 { /* USB1 */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
fsl,usbphy = <&usbphy2>;
status = "disabled";
};
usb@02184400 { /* USB2 */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 41 0x04>;
status = "disabled";
};
usb@02184600 { /* USB3 */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x200>;
interrupts = <0 42 0x04>;
status = "disabled";
};
ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;

View File

@ -842,6 +842,7 @@ config SOC_IMX6Q
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select HAVE_SMP
select MFD_ANATOP
select PINCTRL
select PINCTRL_IMX6Q
select USE_OF

View File

@ -152,7 +152,7 @@ enum mx6q_clks {
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
ssi2_ipg, ssi3_ipg, rom,
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
clk_max
};
@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void)
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
/* name parent_name reg idx */
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
@ -401,6 +404,12 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");

View File

@ -24,6 +24,7 @@
#include <linux/pinctrl/machine.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/anatop.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void)
imx6q_sabrelite_cko1_setup();
}
static void __init imx6q_usb_init(void)
{
struct device_node *np;
struct platform_device *pdev = NULL;
struct anatop *adata = NULL;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
if (np)
pdev = of_find_device_by_node(np);
if (pdev)
adata = platform_get_drvdata(pdev);
if (!adata) {
if (np)
of_node_put(np);
return;
}
#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
/*
* The external charger detector needs to be disabled,
* or the signal at DP will be poor
*/
anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
BM_ANADIG_USB_CHRG_DETECT_EN_B
| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
~0);
anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
BM_ANADIG_USB_CHRG_DETECT_EN_B |
BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
~0);
of_node_put(np);
}
static void __init imx6q_init_machine(void)
{
/*
@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
imx6q_pm_init();
imx6q_usb_init();
}
static void __init imx6q_map_io(void)