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clk: qcom: Add lpass clock controller driver for SDM845 

Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered
with the clock framework based on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Taniya Das 2018-11-30 23:51:29 +05:30 committed by Stephen Boyd
parent 8ff1a156cb
commit 8d3e5b9c1f
4 changed files with 224 additions and 0 deletions
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9
drivers/clk/qcom/Kconfig
View File

@ -293,6 +293,15 @@ config SDM_DISPCC_845
Say Y if you want to support display devices and functionality such as
splash screen.
config SDM_LPASSCC_845
tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller"
depends on COMMON_CLK_QCOM
select SDM_GCC_845
help
Support for the LPASS clock controller on SDM845 devices.
Say Y if you want to use the LPASS branch clocks of the LPASS clock
controller to reset the LPASS subsystem.
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST

1
drivers/clk/qcom/Makefile
View File

@ -46,6 +46,7 @@ obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o

35
drivers/clk/qcom/gcc-sdm845.c
View File

@ -3153,6 +3153,37 @@ static struct clk_branch gcc_cpuss_gnoc_clk = {
},
};
/* TODO: Remove after DTS updated to protect these */
#ifdef CONFIG_SDM_LPASSCC_845
static struct clk_branch gcc_lpass_q6_axi_clk = {
.halt_reg = 0x47000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_sway_clk = {
.halt_reg = 0x47008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_sway_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
#endif
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
@ -3453,6 +3484,10 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
#ifdef CONFIG_SDM_LPASSCC_845
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
#endif
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {

179
drivers/clk/qcom/lpasscc-sdm845.c Normal file
View File

@ -0,0 +1,179 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
.halt_reg = 0x12000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x12000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbm_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_q6ss_ahbs_aon_clk = {
.halt_reg = 0x1f000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x1f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbs_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_core_clk = {
.halt_reg = 0x20,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_xo_clk = {
.halt_reg = 0x38,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x38,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_sleep_clk = {
.halt_reg = 0x3c,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct regmap_config lpass_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
[LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
[LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
};
static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
.config = &lpass_regmap_config,
.clks = lpass_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
};
static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
};
static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
.config = &lpass_regmap_config,
.clks = lpass_qdsp6ss_sdm845_clocks,
.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
};
static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
const struct qcom_cc_desc *desc)
{
struct regmap *regmap;
struct resource *res;
void __iomem *base;
res = platform_get_resource(pdev, IORESOURCE_MEM, index);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, desc, regmap);
}
static int lpass_cc_sdm845_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
int ret;
lpass_regmap_config.name = "cc";
desc = &lpass_cc_sdm845_desc;
ret = lpass_clocks_sdm845_probe(pdev, 0, desc);
if (ret)
return ret;
lpass_regmap_config.name = "qdsp6ss";
desc = &lpass_qdsp6ss_sdm845_desc;
return lpass_clocks_sdm845_probe(pdev, 1, desc);
}
static const struct of_device_id lpass_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-lpasscc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table);
static struct platform_driver lpass_cc_sdm845_driver = {
.probe = lpass_cc_sdm845_probe,
.driver = {
.name = "sdm845-lpasscc",
.of_match_table = lpass_cc_sdm845_match_table,
},
};
static int __init lpass_cc_sdm845_init(void)
{
return platform_driver_register(&lpass_cc_sdm845_driver);
}
subsys_initcall(lpass_cc_sdm845_init);
static void __exit lpass_cc_sdm845_exit(void)
{
platform_driver_unregister(&lpass_cc_sdm845_driver);
}
module_exit(lpass_cc_sdm845_exit);
MODULE_DESCRIPTION("QTI LPASS_CC SDM845 Driver");
MODULE_LICENSE("GPL v2");